From nobody Sat Nov 23 21:52:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.libvirt.org designates 8.43.85.245 as permitted sender) client-ip=8.43.85.245; envelope-from=devel-bounces@lists.libvirt.org; helo=lists.libvirt.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of lists.libvirt.org designates 8.43.85.245 as permitted sender) smtp.mailfrom=devel-bounces@lists.libvirt.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.libvirt.org (lists.libvirt.org [8.43.85.245]) by mx.zohomail.com with SMTPS id 1731080720688246.20775606490338; Fri, 8 Nov 2024 07:45:20 -0800 (PST) Received: by lists.libvirt.org (Postfix, from userid 996) id 797661752; Fri, 8 Nov 2024 10:45:19 -0500 (EST) Received: from lists.libvirt.org (localhost [IPv6:::1]) by lists.libvirt.org (Postfix) with ESMTP id D71D9175D; Fri, 8 Nov 2024 10:43:50 -0500 (EST) Received: by lists.libvirt.org (Postfix, from userid 996) id F168916F6; Fri, 8 Nov 2024 10:43:46 -0500 (EST) Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.libvirt.org (Postfix) with ESMTPS id BA1A016F6 for ; Fri, 8 Nov 2024 10:43:35 -0500 (EST) Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-43158625112so20585175e9.3 for ; Fri, 08 Nov 2024 07:43:35 -0800 (PST) Received: from localhost.localdomain ([89.101.134.25]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381ed97ce1bsm5240064f8f.36.2024.11.08.07.43.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 08 Nov 2024 07:43:34 -0800 (PST) X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on lists.libvirt.org X-Spam-Level: X-Spam-Status: No, score=-0.5 required=5.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED,SPF_HELO_NONE autolearn=unavailable autolearn_force=no version=3.4.4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731080614; x=1731685414; darn=lists.libvirt.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jcB7qkOMOiyB8tsoussWhpdxJCkkhiJl/8TU9dtEiFk=; b=AwlsXlxgAm2laRy9gfYkIXOKwsGLKD7IWVTR0EV9HPYEBvyawFgZS8nwDqD4h8fvb8 N+HyRKHcj8YcAlY4VlAy0+8IcAWQBA8FWa+XslZAFYk9uBLfJbwsH6m/tvKqk31h8sBj aO59pM21J7JAZGwikUqhgRiappC1mPGrTwBpzbY7k6xAGTJWg6/ArkwUa5BsHcOMUirb wEGsodGmukpTkt4kIOIgMu+cIE0Y3Yb1P7cssPfiprWUzpKhpppB9PYFZEnx5ZrjoUb9 BhGjMhO0++XN+iEqsCEGmCpC6OSSkWhPi6BN3T1lqFTRoB787GppAg5W9/egzDUMGXEJ fMRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731080614; x=1731685414; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jcB7qkOMOiyB8tsoussWhpdxJCkkhiJl/8TU9dtEiFk=; b=nigzxRbAsDzV5pnAu8UBxNeU+7wS2001Z8diTX1nMhE3xhazfJGCMLwCOwIxNSPWnb JaM252ewKMbQePca6K7RVZBYShfFJh0zqcBShobPsvhyquV5HQ1XSP2as+1B/GSUdncR mdrpt3rj1ADGvRs18f5sJdvKZP6Rx+yacUSNzW2/f5knttN83bpzjj2y/yDPoxGWx08f DB0WBGmAbxvhEmEV4oBHnIVP5P09rV1B3CSSyLvTIdMs8IKfwtSGi/Zm640JxA99Ds6e +N86gXhU2hs9xkmQwcxeJfy4kHGVQLMyzJ+XIE4yBVkf8ZLteimjdfnUAkUQsIQK+ySl b3lQ== X-Forwarded-Encrypted: i=1; AJvYcCWMDPCq0k9p07WdVLGO3LEXQwrDaTtaAhcbmjLDZ+ARk+QTI5wxVYQ39SZLH0K9rCWZkc9usA==@lists.libvirt.org X-Gm-Message-State: AOJu0YxZNfSDlejuosrND9kowaNhlbNqcf5tFYYmCeCASzycuy6Zq+MQ GAq6PEk4msL4ElXFGUw8/tHpo8ZZ4bctfk1Bxo5GY8oLSobSdfV+EX9cwpx1npw= X-Google-Smtp-Source: AGHT+IE5iJpgAN3QbQFbsTkTTtKML5XnMdcX0mMfdR6XqjfZFb+DA+e4v4caq1c+jtSs8x4YVFs6Mw== X-Received: by 2002:a05:600c:510a:b0:430:5846:7582 with SMTP id 5b1f17b1804b1-432b74fda3dmr27458515e9.7.1731080614485; Fri, 08 Nov 2024 07:43:34 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Subject: [PATCH v3 03/17] hw/intc/xilinx_intc: Make device endianness configurable Date: Fri, 8 Nov 2024 15:43:03 +0000 Message-ID: <20241108154317.12129-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241108154317.12129-1-philmd@linaro.org> References: <20241108154317.12129-1-philmd@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-ID-Hash: S2VPIHXF3TSOZG5CI76TJR73YOJYIBXH X-Message-ID-Hash: S2VPIHXF3TSOZG5CI76TJR73YOJYIBXH X-MailFrom: philmd@linaro.org X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-config-1; header-match-config-2; header-match-config-3; header-match-devel.lists.libvirt.org-0 CC: Jason Wang , Paolo Bonzini , Richard Henderson , devel@lists.libvirt.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , "Edgar E. Iglesias" , Thomas Huth , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Peter Maydell , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= X-Mailman-Version: 3.2.2 Precedence: list List-Id: Development discussions about the libvirt library & tools Archived-At: List-Archive: List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1731080723039116600 Content-Type: text/plain; charset="utf-8" Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness for each machine using the device. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/xilinx_intc.c | 52 +++++++++++++++++------- hw/microblaze/petalogix_ml605_mmu.c | 1 + hw/microblaze/petalogix_s3adsp1800_mmu.c | 1 + 3 files changed, 40 insertions(+), 14 deletions(-) diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index 8fb6b4f1a5..fc55c8afca 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -3,6 +3,9 @@ * * Copyright (c) 2009 Edgar E. Iglesias. * + * https://docs.amd.com/v/u/en-US/xps_intc + * DS572: LogiCORE IP XPS Interrupt Controller (v2.01a) + * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal * in the Software without restriction, including without limitation the r= ights @@ -49,6 +52,7 @@ struct XpsIntc { SysBusDevice parent_obj; =20 + bool little_endian_model; MemoryRegion mmio; qemu_irq parent_irq; =20 @@ -140,18 +144,29 @@ static void pic_write(void *opaque, hwaddr addr, update_irq(p); } =20 -static const MemoryRegionOps pic_ops =3D { - .read =3D pic_read, - .write =3D pic_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .impl =3D { - .min_access_size =3D 4, - .max_access_size =3D 4, +static const MemoryRegionOps pic_ops[2] =3D { + [0 ... 1] =3D { + .read =3D pic_read, + .write =3D pic_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + /* + * All XPS INTC registers are accessed through the PLB interfa= ce. + * The base address for these registers is provided by the + * configuration parameter, C_BASEADDR. Each register is 32 bi= ts + * although some bits may be unused and is accessed on a 4-byte + * boundary offset from the base address. + */ + .min_access_size =3D 4, + .max_access_size =3D 4, + }, }, - .valid =3D { - .min_access_size =3D 4, - .max_access_size =3D 4 - } + [0].endianness =3D DEVICE_BIG_ENDIAN, + [1].endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 static void irq_handler(void *opaque, int irq, int level) @@ -174,13 +189,21 @@ static void xilinx_intc_init(Object *obj) =20 qdev_init_gpio_in(DEVICE(obj), irq_handler, 32); sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq); - - memory_region_init_io(&p->mmio, obj, &pic_ops, p, "xlnx.xps-intc", - R_MAX * 4); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio); } =20 +static void xilinx_intc_realize(DeviceState *dev, Error **errp) +{ + XpsIntc *p =3D XILINX_INTC(dev); + + memory_region_init_io(&p->mmio, OBJECT(dev), + &pic_ops[p->little_endian_model], + p, "xlnx.xps-intc", + R_MAX * 4); +} + static Property xilinx_intc_properties[] =3D { + DEFINE_PROP_BOOL("little-endian", XpsIntc, little_endian_model, true), DEFINE_PROP_UINT32("kind-of-intr", XpsIntc, c_kind_of_intr, 0), DEFINE_PROP_END_OF_LIST(), }; @@ -189,6 +212,7 @@ static void xilinx_intc_class_init(ObjectClass *klass, = void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 + dc->realize =3D xilinx_intc_realize; device_class_set_props(dc, xilinx_intc_properties); } =20 diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_= ml605_mmu.c index d2b2109065..64e8cadbee 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -111,6 +111,7 @@ petalogix_ml605_init(MachineState *machine) =20 =20 dev =3D qdev_new("xlnx.xps-intc"); + qdev_prop_set_bit(dev, "little-endian", true); qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petal= ogix_s3adsp1800_mmu.c index 8110be8371..af949196d3 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -95,6 +95,7 @@ petalogix_s3adsp1800_init(MachineState *machine) 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); =20 dev =3D qdev_new("xlnx.xps-intc"); + qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); qdev_prop_set_uint32(dev, "kind-of-intr", 1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); --=20 2.45.2