From nobody Sat Nov 23 22:46:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1731070641; cv=none; d=zohomail.com; s=zohoarc; b=eDqD4po6k82VeZkFocU2HsCe3qSoqDlHAFEFn20UHKgs5jY9uoPW5MOQ1BCicgFQDVsu28z900gn0pRmovOXGNa1+jpnklAJjHQms23+HK6zaMR5hRsx+BLCX20fFUql/NC6T45zPabEClyHAdkj9a4nWrunq/onynNe52C6X08= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1731070641; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=yWLARnJsHwzS0RgHIcI77DKVokvLa1GChhDiTojj2Xw=; b=TETwddVsDw78pc/4V0X6uMiZ4kYdvZna5i6rLXYSMURMgOBxYrNNqOSPONTJ8P+9io/fFfFXZ4u8EiLEHFIu1/Am5wkoEo44yotkXblyJcIeqlPi71HgkOSRun8iD3W7vI977/uDL0wZ0joIKFh/t2v66RrNI4i1sGhbE3VrEmU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1731070641450893.9068302843863; Fri, 8 Nov 2024 04:57:21 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t9OXD-00052P-JY; Fri, 08 Nov 2024 07:56:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t9OXB-00052D-VD; Fri, 08 Nov 2024 07:56:17 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t9OX9-0006hA-Dk; Fri, 08 Nov 2024 07:56:17 -0500 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4XlJmk4FBfz6K9Yp; Fri, 8 Nov 2024 20:54:30 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 8AFB1140CF4; Fri, 8 Nov 2024 20:56:13 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 8 Nov 2024 13:56:07 +0100 To: , CC: , , , , , , , , , Subject: [RFC PATCH 4/5] hw/arm/virt-acpi-build: Build IORT with multiple SMMU nodes Date: Fri, 8 Nov 2024 12:52:41 +0000 Message-ID: <20241108125242.60136-5-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20241108125242.60136-1-shameerali.kolothum.thodi@huawei.com> References: <20241108125242.60136-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1731070643446116600 From: Nicolin Chen Now that=C2=A0we can have multiple user-creatable smmuv3-nested devices, each associated=C2=A0with different pci buses, update IORT ID mappings accordingly. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/virt-acpi-build.c | 34 ++++++++++++++++++++++++---------- include/hw/arm/virt.h | 6 ++++++ 2 files changed, 30 insertions(+), 10 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index e10cad86dd..ec4cdfb2d7 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -276,8 +276,10 @@ static void build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { int i, nb_nodes, rc_mapping_count; - size_t node_size, smmu_offset =3D 0; + size_t node_size, *smmu_offset; AcpiIortIdMapping *idmap; + hwaddr base; + int irq, num_smmus =3D 0; uint32_t id =3D 0; GArray *smmu_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMapp= ing)); GArray *its_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMappi= ng)); @@ -287,7 +289,21 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) /* Table 2 The IORT */ acpi_table_begin(&table, table_data); =20 - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { + if (vms->smmu_nested_count) { + irq =3D vms->irqmap[VIRT_SMMU_NESTED] + ARM_SPI_BASE; + base =3D vms->memmap[VIRT_SMMU_NESTED].base; + num_smmus =3D vms->smmu_nested_count; + } else if (virt_has_smmuv3(vms)) { + irq =3D vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; + base =3D vms->memmap[VIRT_SMMU].base; + num_smmus =3D 1; + } + + smmu_offset =3D g_new0(size_t, num_smmus); + nb_nodes =3D 2; /* RC, ITS */ + nb_nodes +=3D num_smmus; /* SMMU nodes */ + + if (virt_has_smmuv3(vms)) { AcpiIortIdMapping next_range =3D {0}; =20 object_child_foreach_recursive(object_get_root(), @@ -317,10 +333,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) g_array_append_val(its_idmaps, next_range); } =20 - nb_nodes =3D 3; /* RC, ITS, SMMUv3 */ rc_mapping_count =3D smmu_idmaps->len + its_idmaps->len; } else { - nb_nodes =3D 2; /* RC, ITS */ rc_mapping_count =3D 1; } /* Number of IORT Nodes */ @@ -342,10 +356,9 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) /* GIC ITS Identifier Array */ build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4); =20 - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { - int irq =3D vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; + for (i =3D 0; i < num_smmus; i++) { + smmu_offset[i] =3D table_data->len - table.table_offset; =20 - smmu_offset =3D table_data->len - table.table_offset; /* Table 9 SMMUv3 Format */ build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type = */ node_size =3D SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE; @@ -356,7 +369,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) /* Reference to ID Array */ build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4); /* Base address */ - build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base,= 8); + build_append_int_noprefix(table_data, base + (i * SMMU_IO_LEN), 8); /* Flags */ build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ @@ -367,6 +380,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */ build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */ build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */ + irq +=3D NUM_SMMU_IRQS; build_append_int_noprefix(table_data, 0, 4); /* Proximity domain */ /* DeviceID mapping index (ignored since interrupts are GSIV based= ) */ build_append_int_noprefix(table_data, 0, 4); @@ -405,7 +419,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, 0, 3); /* Reserved */ =20 /* Output Reference */ - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { + if (virt_has_smmuv3(vms)) { AcpiIortIdMapping *range; =20 /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */ @@ -413,7 +427,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) range =3D &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); /* output IORT node is the smmuv3 node */ build_iort_id_mapping(table_data, range->input_base, - range->id_count, smmu_offset); + range->id_count, smmu_offset[i]); } =20 /* bypassed RIDs connect to ITS group node directly: RC -> ITS */ diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 50e47a4ef3..304ab134ae 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -219,4 +219,10 @@ static inline int virt_gicv3_redist_region_count(VirtM= achineState *vms) vms->highmem_redists) ? 2 : 1; } =20 +static inline bool virt_has_smmuv3(const VirtMachineState *vms) +{ + return vms->iommu =3D=3D VIRT_IOMMU_SMMUV3 || + vms->iommu =3D=3D VIRT_IOMMU_SMMUV3_NESTED; +} + #endif /* QEMU_ARM_VIRT_H */ --=20 2.34.1