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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e99a541da0sm5540135a91.13.2024.11.08.00.50.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2024 00:50:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1731055826; x=1731660626; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CjPXxhHgkURlI8UX1KuKe1nxTTSvfnRKKrN/i3Rc46w=; b=BGtmdXnVKArdFT1QPSXiy5fiWNgFvyAg37IvIjme7oI1EVfCqjpF99PZKQVahP5tnF PV0pxyZXMO2GSGisMhHjlGnCSS4Pym/AJZeOxzWO5rqGDWFzSGh5BGbEuz41XPNC6ZeP 4Lzd6mxXhcrCdN53XnwCrQnA3EcO8ReVs8OAgtpDqXz2ICFAScbbPgSIKiYfT++XgoTO JKQ9RFivyeOlg/6FuPySttjQxU9wUQIhf1bnRkiIdr+hlmZxUKid4KbB3HGBxYg0bQb+ Wyc/QNGkda0TW3hW6qoq9h2QL6sVehFEiR/im+PV9wMJ2tSLDx4EIvpVRlg43aw3KwO/ DdMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731055826; x=1731660626; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CjPXxhHgkURlI8UX1KuKe1nxTTSvfnRKKrN/i3Rc46w=; b=Ny9XtB6K8e42p1+MRXQlnosV2QS2EYMVxoScepr5JUC7yTeH0631zQAUZOe3i9wxbI faRlOAwI6a1TkxeztIRW7iDNEb6R3unz0fhmibQfSwE2dhQ2QWByWR1xKP4f0q2wuZm/ 2BYngii0fe16fn0D/QFw3YK/TkzuqVXPKwdZeAZthuw7tAVStA1BXfPwRpSqk+uqvw2R vVVNIT4gylucFJbbdafXncGjUO4ocoPp2QjGBh7bJCfQHNAPdN+o6VIKf0EDA8RCB7xs pCyd5cNPie88JEBItddZJ4vNkuUpWoADAeeScTvJnInuFhzTm3x3gbLHSyAbshWQVJFA 1dhg== X-Gm-Message-State: AOJu0Yw2ffujkyOvWqrhlsHPLbNzCpgHeQitYLFydN3tmK0xEer7JoNt RP5MMTY5kxYuOQ35efQBKVrx2acZpz5PH55TAWpdyNyI7zRt/8TX6qsTp2ziDBLFvk1wdqwlbPE wq2mjrEy4zhS78NjkTMjU7949qVGOHddpD4zu5a2V0QT8dvK15xsBC6PsX9bQBFTNUTH0jgsoVp 7eMUcY8gVYYCg2kw6NyMK+CzVQQ+XaEhvW7Cg= X-Google-Smtp-Source: AGHT+IF98wvlR++RvwmJqJQ+2bT6A+fJGUqbJwK3jwwx76w4Eou4mdzxk8M70TwNzlfUrPA+YJJn/w== X-Received: by 2002:a05:6a21:3418:b0:1d9:261c:5943 with SMTP id adf61e73a8af0-1dc2296b919mr2538588637.10.1731055825984; Fri, 08 Nov 2024 00:50:25 -0800 (PST) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Fea.Wang" , Frank Chang , Jim Shu Subject: [PATCH v2 4/5] target/riscv: Check memory access to meet svuket rule Date: Fri, 8 Nov 2024 16:52:38 +0800 Message-Id: <20241108085239.2927152-5-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241108085239.2927152-1-fea.wang@sifive.com> References: <20241108085239.2927152-1-fea.wang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=fea.wang@sifive.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1731055942466116600 Content-Type: text/plain; charset="utf-8" Follow the Svukte spec, do the memory access address checking 1. Include instruction fetches or explicit memory accesses 2. System run in effective privilege U or VU 3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if instruction is HLV, HLVX, HSV and excute from U mode to VU mode 4. Depend on Sv39 and check virtual addresses bit[SXLEN-1] 5. Raises a page-fault exception corresponding to the original access type. Ref: https://github.com/riscv/riscv-isa-manual/pull/1564/files Signed-off-by: Frank Chang Signed-off-by: Fea.Wang Reviewed-by: Jim Shu --- target/riscv/cpu_helper.c | 57 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0a3ead69ea..725c049f7a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -857,6 +857,57 @@ static int get_physical_address_pmp(CPURISCVState *env= , int *prot, hwaddr addr, return TRANSLATE_SUCCESS; } =20 +/* + * Return 'true' means no need to do svukte check, or need to do svukte an= d the + * address is valid. Return 'false' means need to do svukte check but addr= ess + * is invalid. + */ +static bool check_svukte_valid(CPURISCVState *env, vaddr addr, + int mode, bool virt) +{ + /* + * Check hstatus.HUKTE if the effective mode is switched to VU-mode by + * executing HLV/HLVX/HSV in U-mode. + * For other cases, check senvcfg.UKTE. + */ + bool ukte; + if (env->priv =3D=3D PRV_U && !env->virt_enabled && virt) { + ukte =3D !!(env->hstatus & HSTATUS_HUKTE); + } else { + ukte =3D !!(env->senvcfg & SENVCFG_UKTE); + } + + if (VM_1_10_SV39 !=3D get_field(env->satp, SATP64_MODE)) { + /* Svukte extension depends on Sv39. */ + return true; + } + + /* + * Svukte extension is qualified only in U or VU-mode. + * + * Effective mode can be switched to U or VU-mode by: + * - M-mode + mstatus.MPRV=3D1 + mstatus.MPP=3DU-mode. + * - Execute HLV/HLVX/HSV from HS-mode + hstatus.SPVP=3D0. + * - U-mode. + * - VU-mode. + * - Execute HLV/HLVX/HSV from U-mode + hstatus.HU=3D1. + */ + if (mode !=3D PRV_U) { + return true; + } + + if (!ukte) { + return true; + } + + uint32_t sxl =3D riscv_cpu_sxl(env); + sxl =3D (sxl =3D=3D 0) ? MXL_RV32 : sxl; + uint32_t sxlen =3D 32 * sxl; + uint64_t high_bit =3D addr & (1UL << (sxlen - 1)); + + return !high_bit; +} + /* * get_physical_address - get the physical address for this virtual address * @@ -894,6 +945,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, MemTxResult res; MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; int mode =3D mmuidx_priv(mmu_idx); + bool virt =3D mmuidx_2stage(mmu_idx); bool use_background =3D false; hwaddr ppn; int napot_bits =3D 0; @@ -901,6 +953,11 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, bool is_sstack_idx =3D ((mmu_idx & MMU_IDX_SS_WRITE) =3D=3D MMU_IDX_SS= _WRITE); bool sstack_page =3D false; =20 + if (env_archcpu(env)->cfg.ext_svukte && first_stage && + !check_svukte_valid(env, addr, mode, virt)) { + return TRANSLATE_FAIL; + } + /* * Check if we should use the background registers for the two * stage translation. We don't need to check if we actually need --=20 2.34.1