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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e99a541da0sm5540135a91.13.2024.11.08.00.50.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2024 00:50:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1731055818; x=1731660618; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m3zF2/6gcrH4Igw1oUoyFWon05IdXK20fHomVyO9faA=; b=ZHEx+79bW6qeRv2UK2Zr2AktPgFbqPrYjcTPf6WL63BxmcCG4+z3ntgPbJVlZpmIfp R/7jp6LwZEvnFs1gXAMuSICRqNBedSx8XQhkIlRZbsb+dz/BS5CEmJiOEKnBtStU/QqZ b9h1Cuo3wo+7aV+8lB8xHVRRM3k2bPAGwdT3+YlFr0UHeHctF2iXWAlBs6DQVPtT2vBE 29SDeivZrIBCvGUvEknp3ELenT5TwyQqcYDS/unZwfoOqq/Zq25oR8FYanLYlDOiYb3P TPO2Y91c7GbxWPLfUB84S5iBm6MrW2lzf0FGst1gikX99JIaaz29ULWwxK1O3b3XMmXJ bHQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731055818; x=1731660618; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m3zF2/6gcrH4Igw1oUoyFWon05IdXK20fHomVyO9faA=; b=NDK3fB7qvTTs32xdni0uV7o74hRmRqTM9MEvv0VcWGySU+pH4MLWB6enkt5BIgXt8K bz44n+bVp+fbaavQLo/MfdaKy8sHcnKaXfaTUzsBdHMtJqPPn94y17eiZAYJE+j1KPtx wRw9qJKc3PV+nsm2vhLIdrlqDnoOEeHEmj28mzcFxccrWsL52943aKQ9IKMrcNHMJIyH C8D6NdUL2Q0GJBmCuqgLuWZVZMCwzm1iEe+pyDiA4i5NvaWWxBb4J/NK8UNz+Ba4txvb 3tUv5GrvppAzAkkgLXXmTjQge642XjAwbOeiNrMeDCeafhhaxgBjJHaOE4vbY5QMNKuZ l+Dg== X-Gm-Message-State: AOJu0YzwBW4ue6PDcNSCDXf0GovjFUA5LGXIO2Sw0kwV4LY8rtRZFvXr j89NvJlFrPhaiai6V7+2FfnhX4QARg6/YOPeyfu+Y6QSRhYL2iCHnFEidT71sbQ9bZ1WhWag0Ax oM//2jVi2nbRwHnJzm+0/bK55y20gnPTX9HlofDv7cj9RFVS/vflApRPomshpFIpdnwY+7iTxaV uHtYHe8nad3/se3r2WtMwtVSgY1xQb6RWEjM4= X-Google-Smtp-Source: AGHT+IEtuZ8Q3o90cjh5SCjh3IUtFmlydRCaqsaMMW4Eih7b0fEDJNmHM5NfpxpBR9T09eESF9s89g== X-Received: by 2002:a17:90b:4f43:b0:2e2:e82d:48cf with SMTP id 98e67ed59e1d1-2e9b1724271mr3086133a91.16.1731055818318; Fri, 08 Nov 2024 00:50:18 -0800 (PST) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Fea.Wang" , Frank Chang , Jim Shu Subject: [PATCH v2 2/5] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled Date: Fri, 8 Nov 2024 16:52:36 +0800 Message-Id: <20241108085239.2927152-3-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241108085239.2927152-1-fea.wang@sifive.com> References: <20241108085239.2927152-1-fea.wang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=fea.wang@sifive.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1731055936387116600 Content-Type: text/plain; charset="utf-8" Svukte extension add UKTE bit, bit[8] in senvcfg CSR. The bit will be supported when the svukte extension is enabled. When senvcfg[UKTE] bit is set, the memory access from U-mode should do the svukte check only except HLV/HLVX/HSV H-mode instructions which depend on hstatus[HUKTE]. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 385a2c67c2..4b9f899217 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -785,6 +785,7 @@ typedef enum RISCVException { #define SENVCFG_CBIE MENVCFG_CBIE #define SENVCFG_CBCFE MENVCFG_CBCFE #define SENVCFG_CBZE MENVCFG_CBZE +#define SENVCFG_UKTE BIT(8) =20 #define HENVCFG_FIOM MENVCFG_FIOM #define HENVCFG_LPE MENVCFG_LPE diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9846770820..1936a6f32a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2453,6 +2453,10 @@ static RISCVException write_senvcfg(CPURISCVState *e= nv, int csrno, mask |=3D SENVCFG_SSE; } =20 + if (env_archcpu(env)->cfg.ext_svukte) { + mask |=3D SENVCFG_UKTE; + } + env->senvcfg =3D (env->senvcfg & ~mask) | (val & mask); return RISCV_EXCP_NONE; } --=20 2.34.1