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[219.106.231.132]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7f41f65d358sm2326435a12.84.2024.11.07.19.30.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Nov 2024 19:30:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=igel-co-jp.20230601.gappssmtp.com; s=20230601; t=1731036624; x=1731641424; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZEmXhN0e4yofB9St5S3+HcVTsbiOBljTRevzyH0DrDI=; b=ory0/elUCxf/vrmGSKz3hnclJvn+NPb/1/iI8JCJJebzR3on0zZvaFADOl9bXQeX2B sJOLjvlY3nT6+wWiUj/rM/A9GPH6kPNMRDHQ5dDd8ubKPsmeuXSaeALKHv03x676pUe0 b5Znba2osYTzI/UWtRP1mWbVIxXIUUeIPWhkA1D1L7adXMj71PdT811qwYEdk3LnHljP fyQhpHiIsazzXGjEEMgFrol/Ukj7W90JNAA/ZQFo6E9/jJE7+hyOY/O7CpL4wzbKKGGb dXji5kAsVhP495/Ri8GHXlxuQTim22D25e2CnTALSmsm5Eg5il1CvuEZ1JTCo1djYG3H daJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731036624; x=1731641424; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZEmXhN0e4yofB9St5S3+HcVTsbiOBljTRevzyH0DrDI=; b=tuPelUvjmIkOrX4aBSP9dy8f6ghGBHvv7GSBv1RkXmI0ORuny/MY4jfG53od/4zA52 R4AsEuvCOrWfCcA9tlPC7iEJvsZZkQrhLgT6zwOekI2xm/o87hV62v/WkJYT6REffzW0 VT3KuaWtRhnCDP5ImKR7nrLcZ6bqEkroV7y/BexiztYQ8wVx7zHPrBZj9m2ygguxAdA5 f9apvOQrRF0iooZlyBsy/JE4g1mYJHtfsO4NXRxmpa2V12ZZ3XqreUqQFhI0zItQRgdk 7LkjL7al8h3n/vlF5CG2EK4Fpdx0uY0Lhf++YzYba85WTdm3RKqbVLfvXglhcXLLmIJa n3bw== X-Gm-Message-State: AOJu0Yy0r6cDtIr3pSo/1T88xWJqLEsyt1OEfzesdF5ywslPiwKAsAjQ F4HoNiW27/gHMtCECe5QS2Vmtz4yT1bK0/taor2+apidWYvU3FGMlu/9DkxT0ZIqbY3zk49iTo9 kN7Q= X-Google-Smtp-Source: AGHT+IH8Cu8BmQ2H1pYCF1MhqZHlWXBnPlF4+KiVNOByoEJ9C4HHxEoU0/lhjDRoVgya92wPthhJcA== X-Received: by 2002:a05:6808:118c:b0:3e6:5f3:dadb with SMTP id 5614622812f47-3e794705982mr1776028b6e.39.1731036623668; Thu, 07 Nov 2024 19:30:23 -0800 (PST) From: Tomoyuki HIROSE To: qemu-devel@nongnu.org Cc: Tomoyuki HIROSE , Paolo Bonzini , Peter Xu , David Hildenbrand , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 2/5] system/memory: support unaligned access Date: Fri, 8 Nov 2024 12:29:46 +0900 Message-ID: <20241108032952.56692-3-tomoyuki.hirose@igel.co.jp> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241108032952.56692-1-tomoyuki.hirose@igel.co.jp> References: <20241108032952.56692-1-tomoyuki.hirose@igel.co.jp> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=tomoyuki.hirose@igel.co.jp; helo=mail-oi1-x22a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @igel-co-jp.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1731036681077116600 Content-Type: text/plain; charset="utf-8" The previous code ignored 'impl.unaligned' and handled unaligned accesses as is. But this implementation could not emulate specific registers of some devices that allow unaligned access such as xHCI Host Controller Capability Registers. This commit emulates an unaligned access with multiple aligned accesses. Additionally, the overwriting of the max access size is removed to retrive the actual max access size. Signed-off-by: Tomoyuki HIROSE --- system/memory.c | 147 ++++++++++++++++++++++++++++++++++++++--------- system/physmem.c | 8 --- 2 files changed, 119 insertions(+), 36 deletions(-) diff --git a/system/memory.c b/system/memory.c index 85f6834cb3..c2164e6478 100644 --- a/system/memory.c +++ b/system/memory.c @@ -518,27 +518,118 @@ static MemTxResult memory_region_write_with_attrs_ac= cessor(MemoryRegion *mr, return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs); } =20 +typedef MemTxResult (*MemoryRegionAccessFn)(MemoryRegion *mr, + hwaddr addr, + uint64_t *value, + unsigned size, + signed shift, + uint64_t mask, + MemTxAttrs attrs); + +static MemTxResult access_emulation(hwaddr addr, + uint64_t *value, + unsigned int size, + unsigned int access_size_min, + unsigned int access_size_max, + MemoryRegion *mr, + MemTxAttrs attrs, + MemoryRegionAccessFn access_fn_read, + MemoryRegionAccessFn access_fn_write, + bool is_write) +{ + hwaddr a; + uint8_t *d; + uint64_t v; + MemTxResult r =3D MEMTX_OK; + bool is_big_endian =3D memory_region_big_endian(mr); + void (*store)(void *, int, uint64_t) =3D is_big_endian ? stn_be_p : st= n_le_p; + uint64_t (*load)(const void *, int) =3D is_big_endian ? ldn_be_p : ldn= _le_p; + size_t access_size =3D MAX(MIN(size, access_size_max), access_size_min= ); + uint64_t access_mask =3D MAKE_64BIT_MASK(0, access_size * 8); + hwaddr round_down =3D mr->ops->impl.unaligned && addr + size <=3D mr->= size ? + 0 : addr % access_size; + hwaddr start =3D addr - round_down; + hwaddr tail =3D addr + size <=3D mr->size ? addr + size : mr->size; + uint8_t data[16] =3D {0}; + g_assert(size <=3D 8); + + for (a =3D start, d =3D data, v =3D 0; a < tail; + a +=3D access_size, d +=3D access_size, v =3D 0) { + r |=3D access_fn_read(mr, a, &v, access_size, 0, access_mask, + attrs); + store(d, access_size, v); + } + if (is_write) { + stn_he_p(&data[round_down], size, load(value, size)); + for (a =3D start, d =3D data; a < tail; + a +=3D access_size, d +=3D access_size) { + v =3D load(d, access_size); + r |=3D access_fn_write(mr, a, &v, access_size, 0, access_mask, + attrs); + } + } else { + store(value, size, ldn_he_p(&data[round_down], size)); + } + + return r; +} + +static bool is_access_fastpath(hwaddr addr, + unsigned int size, + unsigned int access_size_min, + unsigned int access_size_max, + MemoryRegion *mr) +{ + size_t access_size =3D MAX(MIN(size, access_size_max), access_size_min= ); + hwaddr round_down =3D mr->ops->impl.unaligned && addr + size <=3D mr->= size ? + 0 : addr % access_size; + + return round_down =3D=3D 0 && access_size <=3D size; +} + +static MemTxResult access_fastpath(hwaddr addr, + uint64_t *value, + unsigned int size, + unsigned int access_size_min, + unsigned int access_size_max, + MemoryRegion *mr, + MemTxAttrs attrs, + MemoryRegionAccessFn fastpath) +{ + MemTxResult r =3D MEMTX_OK; + size_t access_size =3D MAX(MIN(size, access_size_max), access_size_min= ); + uint64_t access_mask =3D MAKE_64BIT_MASK(0, access_size * 8); + + if (memory_region_big_endian(mr)) { + for (size_t i =3D 0; i < size; i +=3D access_size) { + r |=3D fastpath(mr, addr + i, value, access_size, + (size - access_size - i) * 8, access_mask, attrs= ); + } + } else { + for (size_t i =3D 0; i < size; i +=3D access_size) { + r |=3D fastpath(mr, addr + i, value, access_size, + i * 8, access_mask, attrs); + } + } + + return r; +} + static MemTxResult access_with_adjusted_size(hwaddr addr, uint64_t *value, unsigned size, unsigned access_size_min, unsigned access_size_max, - MemTxResult (*access_fn) - (MemoryRegion *mr, - hwaddr addr, - uint64_t *value, - unsigned size, - signed shift, - uint64_t mask, - MemTxAttrs attrs), + MemoryRegionAccessFn access_fn_read, + MemoryRegionAccessFn access_fn_write, + bool is_write, MemoryRegion *mr, MemTxAttrs attrs) { - uint64_t access_mask; - unsigned access_size; - unsigned i; MemTxResult r =3D MEMTX_OK; bool reentrancy_guard_applied =3D false; + MemoryRegionAccessFn access_fn_fastpath =3D + is_write ? access_fn_write : access_fn_read; =20 if (!access_size_min) { access_size_min =3D 1; @@ -560,20 +651,16 @@ static MemTxResult access_with_adjusted_size(hwaddr a= ddr, reentrancy_guard_applied =3D true; } =20 - /* FIXME: support unaligned access? */ - access_size =3D MAX(MIN(size, access_size_max), access_size_min); - access_mask =3D MAKE_64BIT_MASK(0, access_size * 8); - if (memory_region_big_endian(mr)) { - for (i =3D 0; i < size; i +=3D access_size) { - r |=3D access_fn(mr, addr + i, value, access_size, - (size - access_size - i) * 8, access_mask, attrs); - } + if (is_access_fastpath(addr, size, access_size_min, access_size_max, m= r)) { + r |=3D access_fastpath(addr, value, size, + access_size_min, access_size_max, mr, attrs, + access_fn_fastpath); } else { - for (i =3D 0; i < size; i +=3D access_size) { - r |=3D access_fn(mr, addr + i, value, access_size, i * 8, - access_mask, attrs); - } + r |=3D access_emulation(addr, value, size, + access_size_min, access_size_max, mr, attrs, + access_fn_read, access_fn_write, is_write); } + if (mr->dev && reentrancy_guard_applied) { mr->dev->mem_reentrancy_guard.engaged_in_io =3D false; } @@ -1459,13 +1546,15 @@ static MemTxResult memory_region_dispatch_read1(Mem= oryRegion *mr, mr->ops->impl.min_access_size, mr->ops->impl.max_access_size, memory_region_read_accessor, - mr, attrs); + memory_region_write_accessor, + false, mr, attrs); } else { return access_with_adjusted_size(addr, pval, size, mr->ops->impl.min_access_size, mr->ops->impl.max_access_size, memory_region_read_with_attrs_acc= essor, - mr, attrs); + memory_region_write_with_attrs_ac= cessor, + false, mr, attrs); } } =20 @@ -1553,15 +1642,17 @@ MemTxResult memory_region_dispatch_write(MemoryRegi= on *mr, return access_with_adjusted_size(addr, &data, size, mr->ops->impl.min_access_size, mr->ops->impl.max_access_size, - memory_region_write_accessor, mr, - attrs); + memory_region_read_accessor, + memory_region_write_accessor, + true, mr, attrs); } else { return access_with_adjusted_size(addr, &data, size, mr->ops->impl.min_access_size, mr->ops->impl.max_access_size, + memory_region_read_with_attrs_access= or, memory_region_write_with_attrs_acces= sor, - mr, attrs); + true, mr, attrs); } } =20 diff --git a/system/physmem.c b/system/physmem.c index dc1db3a384..ff444140a8 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -2693,14 +2693,6 @@ int memory_access_size(MemoryRegion *mr, unsigned l,= hwaddr addr) access_size_max =3D 4; } =20 - /* Bound the maximum access by the alignment of the address. */ - if (!mr->ops->impl.unaligned) { - unsigned align_size_max =3D addr & -addr; - if (align_size_max !=3D 0 && align_size_max < access_size_max) { - access_size_max =3D align_size_max; - } - } - /* Don't attempt accesses larger than the maximum. */ if (l > access_size_max) { l =3D access_size_max; --=20 2.43.0