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AJvYcCWX6/QWIb46MjGlF7YeURRjGV9SWNhx/mTbXgfUIOXstxqtZuJJ0NBv5eg1j5fGYCJQnP/wSw==@lists.libvirt.org X-Gm-Message-State: AOJu0Yw1TzUKzLz9XJ/pjd3+xvsPkIulGGKJzHFVZtUWMYLS5prSwbJ5 49ZeAKmmVwb9keDaVbighms+vooy5Pu83AJ2+B2CFiJLKWLyx+3i5L67ZqTD3rs= X-Google-Smtp-Source: AGHT+IFmvuDn80/qJZJ0/3+MGoYVqXc9lTQbgEvElc+t8ldwX/W7PeKqgXuxIlWkYJlDfusLVItldw== X-Received: by 2002:a05:6000:71a:b0:37d:4e03:ff8e with SMTP id ffacd0b85a97d-381edaed24cmr211383f8f.28.1730942571912; Wed, 06 Nov 2024 17:22:51 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Anton Johansson , qemu-devel@nongnu.org Subject: [RFC PATCH v2 04/16] hw/net/xilinx_ethlite: Simplify by having configurable endianness Date: Thu, 7 Nov 2024 01:22:10 +0000 Message-ID: <20241107012223.94337-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107012223.94337-1-philmd@linaro.org> References: <20241107012223.94337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-ID-Hash: MKDBFJAHRJRS4XJJV4SAHXHA35FTZQQW X-Message-ID-Hash: MKDBFJAHRJRS4XJJV4SAHXHA35FTZQQW X-MailFrom: philmd@linaro.org X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-config-1; header-match-config-2; header-match-config-3; header-match-devel.lists.libvirt.org-0 CC: Paolo Bonzini , Thomas Huth , Jason Wang , devel@lists.libvirt.org, qemu-ppc@nongnu.org, Alistair Francis , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , "Edgar E. Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= X-Mailman-Version: 3.2.2 Precedence: list List-Id: Development discussions about the libvirt library & tools Archived-At: List-Archive: List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1730942686611116600 Content-Type: text/plain; charset="utf-8" The Xilinx 'ethlite' device was added in commit b43848a100 ("xilinx: Add ethlite emulation"), being only built back then for a big-endian MicroBlaze target (see commit 72b675caac "microblaze: Hook into the build-system"). I/O endianness access was then clarified in commit d48751ed4f ("xilinx-ethlite: Simplify byteswapping to/from brams"). Here the 'fix' was to use tswap32(). Since the machine was built as big-endian target, tswap32() use means the fix was for a little endian host. While the datasheet (reference added in file header) is not precise about it, we interpret such change as the device expects accesses in big-endian order. Instead of having a double swapping, one in the core memory layer due to DEVICE_NATIVE_ENDIAN and a second one with the tswap calls, allow the machine code to select the proper endianness desired, removing the need of tswap(). Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness on the single machine using the device. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- RFC until I digest Paolo's review from v1: https://lore.kernel.org/qemu-devel/34f6fe2f-06e0-4e2a-a361-2d662f6814b5@red= hat.com/ --- hw/microblaze/petalogix_s3adsp1800_mmu.c | 2 + hw/net/xilinx_ethlite.c | 54 +++++++++++++++++------- 2 files changed, 40 insertions(+), 16 deletions(-) diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petal= ogix_s3adsp1800_mmu.c index af949196d3..f2e2dc2fd7 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -121,9 +121,11 @@ petalogix_s3adsp1800_init(MachineState *machine) sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); =20 dev =3D qdev_new("xlnx.xps-ethernetlite"); + qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); qemu_configure_nic_device(dev, true, NULL); qdev_prop_set_uint32(dev, "tx-ping-pong", 0); qdev_prop_set_uint32(dev, "rx-ping-pong", 0); + qdev_prop_set_bit(dev, "little-endian-model", !TARGET_BIG_ENDIAN); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]); diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index e84b4cdd35..d2e7939569 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -3,6 +3,9 @@ * * Copyright (c) 2009 Edgar E. Iglesias. * + * DS580: https://docs.amd.com/v/u/en-US/xps_ethernetlite + * LogiCORE IP XPS Ethernet Lite Media Access Controller + * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal * in the Software without restriction, including without limitation the r= ights @@ -25,7 +28,6 @@ #include "qemu/osdep.h" #include "qemu/module.h" #include "qom/object.h" -#include "exec/tswap.h" #include "hw/sysbus.h" #include "hw/irq.h" #include "hw/qdev-properties.h" @@ -60,6 +62,7 @@ struct xlx_ethlite { SysBusDevice parent_obj; =20 + bool little_endian_model; MemoryRegion mmio; qemu_irq irq; NICState *nic; @@ -103,9 +106,10 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) break; =20 default: - r =3D tswap32(s->regs[addr]); + r =3D s->regs[addr]; break; } + return r; } =20 @@ -161,22 +165,37 @@ eth_write(void *opaque, hwaddr addr, break; =20 default: - s->regs[addr] =3D tswap32(value); + s->regs[addr] =3D value; break; } } =20 -static const MemoryRegionOps eth_ops =3D { - .read =3D eth_read, - .write =3D eth_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .impl =3D { - .min_access_size =3D 4, - .max_access_size =3D 4, +static const MemoryRegionOps eth_ops[2] =3D { + { + .read =3D eth_read, + .write =3D eth_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, }, - .valid =3D { - .min_access_size =3D 4, - .max_access_size =3D 4 + { + .read =3D eth_read, + .write =3D eth_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, } }; =20 @@ -237,6 +256,10 @@ static void xilinx_ethlite_realize(DeviceState *dev, E= rror **errp) { struct xlx_ethlite *s =3D XILINX_ETHLITE(dev); =20 + memory_region_init_io(&s->mmio, OBJECT(dev), + ð_ops[s->little_endian_model], s, + "xlnx.xps-ethernetlite", R_MAX * 4); + qemu_macaddr_default_if_unset(&s->conf.macaddr); s->nic =3D qemu_new_nic(&net_xilinx_ethlite_info, &s->conf, object_get_typename(OBJECT(dev)), dev->id, @@ -249,13 +272,12 @@ static void xilinx_ethlite_init(Object *obj) struct xlx_ethlite *s =3D XILINX_ETHLITE(obj); =20 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); - - memory_region_init_io(&s->mmio, obj, ð_ops, s, - "xlnx.xps-ethernetlite", R_MAX * 4); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); } =20 static Property xilinx_ethlite_properties[] =3D { + DEFINE_PROP_BOOL("little-endian", struct xlx_ethlite, + little_endian_model, true), DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, = 1), DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, = 1), DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf), --=20 2.45.2