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Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 01/16] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit Date: Thu, 7 Nov 2024 01:22:07 +0000 Message-ID: <20241107012223.94337-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107012223.94337-1-philmd@linaro.org> References: <20241107012223.94337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730942618594116600 All these MemoryRegionOps read() and write() handlers are implemented expecting 32-bit accesses. Clarify that setting .impl.min/max_access_size fields. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Message-Id: <20241105130431.22564-8-philmd@linaro.org> --- hw/char/xilinx_uartlite.c | 4 ++++ hw/intc/xilinx_intc.c | 4 ++++ hw/net/xilinx_ethlite.c | 4 ++++ hw/timer/xilinx_timer.c | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c index f325084f8b..3022b3d8ef 100644 --- a/hw/char/xilinx_uartlite.c +++ b/hw/char/xilinx_uartlite.c @@ -170,6 +170,10 @@ static const MemoryRegionOps uart_ops =3D { .read =3D uart_read, .write =3D uart_write, .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 4 diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index 6e5012e66e..8fb6b4f1a5 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -144,6 +144,10 @@ static const MemoryRegionOps pic_ops =3D { .read =3D pic_read, .write =3D pic_write, .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index bd81290808..e84b4cdd35 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -170,6 +170,10 @@ static const MemoryRegionOps eth_ops =3D { .read =3D eth_read, .write =3D eth_write, .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index 32a9df69e0..383fc8b3c8 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -193,6 +193,10 @@ static const MemoryRegionOps timer_ops =3D { .read =3D timer_read, .write =3D timer_write, .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 --=20 2.45.2 From nobody Sat Nov 23 21:43:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.libvirt.org designates 8.43.85.245 as permitted sender) client-ip=8.43.85.245; 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AJvYcCVajqqHPTw3BJia8MWoEVaMWIPVxHekucKbbcjZaaMRYW5+l6CGwmYNELhbr+U9atK9zTrxXw==@lists.libvirt.org X-Gm-Message-State: AOJu0YwBG32ZAwKKoHI+i1dHJvwbHWiZsebkQLNzfR3LR5K16Pp6MTYj bzsWoBGAbp8JJ6nmBsUbVXAugWKUJw+JJufhzqdWQ3/dRvzv8Mj19pGBW04n/pY= X-Google-Smtp-Source: AGHT+IHF/9u9vSjDc+iEMUU6zgLXg7t6PjmliJiRoRxwDU3e6wJ2JwVCJkzlXO5nfGZCw6iVBJR1xw== X-Received: by 2002:a05:6000:1fad:b0:37d:5130:b380 with SMTP id ffacd0b85a97d-381c7a5e114mr24972810f8f.23.1730942559815; Wed, 06 Nov 2024 17:22:39 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Anton Johansson , qemu-devel@nongnu.org Subject: [PATCH v2 02/16] hw/microblaze: Propagate CPU endianness to microblaze_load_kernel() Date: Thu, 7 Nov 2024 01:22:08 +0000 Message-ID: <20241107012223.94337-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107012223.94337-1-philmd@linaro.org> References: <20241107012223.94337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-ID-Hash: TGBCK5VHBH55HZU5S37ZJMQZAAFZDYUO X-Message-ID-Hash: TGBCK5VHBH55HZU5S37ZJMQZAAFZDYUO X-MailFrom: philmd@linaro.org X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-config-1; header-match-config-2; header-match-config-3; header-match-devel.lists.libvirt.org-0 CC: Paolo Bonzini , Thomas Huth , Jason Wang , devel@lists.libvirt.org, qemu-ppc@nongnu.org, Alistair Francis , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , "Edgar E. Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Edgar E . Iglesias" X-Mailman-Version: 3.2.2 Precedence: list List-Id: Development discussions about the libvirt library & tools Archived-At: List-Archive: List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1730942620303116600 Content-Type: text/plain; charset="utf-8" Pass vCPU endianness as argument so we can load kernels with different endianness (different from the qemu-system-binary builtin one). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-Id: <20241105130431.22564-9-philmd@linaro.org> Reviewed-by: Richard Henderson --- hw/microblaze/boot.h | 4 ++-- hw/microblaze/boot.c | 8 ++++---- hw/microblaze/petalogix_ml605_mmu.c | 2 +- hw/microblaze/petalogix_s3adsp1800_mmu.c | 2 +- hw/microblaze/xlnx-zynqmp-pmu.c | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/microblaze/boot.h b/hw/microblaze/boot.h index 5a8c2f7975..d179a551a6 100644 --- a/hw/microblaze/boot.h +++ b/hw/microblaze/boot.h @@ -2,8 +2,8 @@ #define MICROBLAZE_BOOT_H =20 =20 -void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base, - uint32_t ramsize, +void microblaze_load_kernel(MicroBlazeCPU *cpu, bool is_little_endian, + hwaddr ddr_base, uint32_t ramsize, const char *initrd_filename, const char *dtb_filename, void (*machine_cpu_reset)(MicroBlazeCPU *)); diff --git a/hw/microblaze/boot.c b/hw/microblaze/boot.c index ed61e483ee..3675489fa5 100644 --- a/hw/microblaze/boot.c +++ b/hw/microblaze/boot.c @@ -114,8 +114,8 @@ static uint64_t translate_kernel_address(void *opaque, = uint64_t addr) return addr - 0x30000000LL; } =20 -void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base, - uint32_t ramsize, +void microblaze_load_kernel(MicroBlazeCPU *cpu, bool is_little_endian, + hwaddr ddr_base, uint32_t ramsize, const char *initrd_filename, const char *dtb_filename, void (*machine_cpu_reset)(MicroBlazeCPU *)) @@ -144,13 +144,13 @@ void microblaze_load_kernel(MicroBlazeCPU *cpu, hwadd= r ddr_base, /* Boots a kernel elf binary. */ kernel_size =3D load_elf(kernel_filename, NULL, NULL, NULL, &entry, NULL, &high, NULL, - TARGET_BIG_ENDIAN, EM_MICROBLAZE, 0, 0); + !is_little_endian, EM_MICROBLAZE, 0, 0); base32 =3D entry; if (base32 =3D=3D 0xc0000000) { kernel_size =3D load_elf(kernel_filename, NULL, translate_kernel_address, NULL, &entry, NULL, NULL, NULL, - TARGET_BIG_ENDIAN, EM_MICROBLAZE, 0, 0); + !is_little_endian, EM_MICROBLAZE, 0, 0); } /* Always boot into physical ram. */ boot_info.bootstrap_pc =3D (uint32_t)entry; diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_= ml605_mmu.c index 61e47d8398..d2b2109065 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -204,7 +204,7 @@ petalogix_ml605_init(MachineState *machine) cpu->cfg.pvr_regs[5] =3D 0xc56be000; cpu->cfg.pvr_regs[10] =3D 0x0e000000; /* virtex 6 */ =20 - microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size, + microblaze_load_kernel(cpu, true, MEMORY_BASEADDR, ram_size, machine->initrd_filename, BINARY_DEVICE_TREE_FILE, NULL); diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petal= ogix_s3adsp1800_mmu.c index 6c0f5c6c65..8110be8371 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -129,7 +129,7 @@ petalogix_s3adsp1800_init(MachineState *machine) =20 create_unimplemented_device("xps_gpio", GPIO_BASEADDR, 0x10000); =20 - microblaze_load_kernel(cpu, ddr_base, ram_size, + microblaze_load_kernel(cpu, !TARGET_BIG_ENDIAN, ddr_base, ram_size, machine->initrd_filename, BINARY_DEVICE_TREE_FILE, NULL); diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pm= u.c index 567aad47bf..bdbf7328bf 100644 --- a/hw/microblaze/xlnx-zynqmp-pmu.c +++ b/hw/microblaze/xlnx-zynqmp-pmu.c @@ -172,7 +172,7 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine) qdev_realize(DEVICE(pmu), NULL, &error_fatal); =20 /* Load the kernel */ - microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR, + microblaze_load_kernel(&pmu->cpu, true, XLNX_ZYNQMP_PMU_RAM_ADDR, machine->ram_size, machine->initrd_filename, machine->dtb, --=20 2.45.2 From nobody Sat Nov 23 21:43:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1730942609; cv=none; d=zohomail.com; s=zohoarc; b=G4aORqpRG09l7/+xU/taeNOvsqKDFJ9LTmSO1sfPtXgu1dNHEh2s9X+skBbS3ALYnV2b2CYpMCLa9d9rHVoWA5KhXKuICttSJHQ18fCbdtZkXgfkvz/0lQpRg2tFaAQSvK8XlBRJ+6pkbUtBdV4x67APpP3cM4oGN4OKcPPPnys= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730942609; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 06 Nov 2024 17:22:46 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Anton Johansson , qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Jason Wang , devel@lists.libvirt.org, qemu-ppc@nongnu.org, Alistair Francis , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , "Edgar E. Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 03/16] hw/intc/xilinx_intc: Make device endianness configurable Date: Thu, 7 Nov 2024 01:22:09 +0000 Message-ID: <20241107012223.94337-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107012223.94337-1-philmd@linaro.org> References: <20241107012223.94337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730942610554116600 Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness for each machine using the device. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/intc/xilinx_intc.c | 61 +++++++++++++++++++----- hw/microblaze/petalogix_ml605_mmu.c | 1 + hw/microblaze/petalogix_s3adsp1800_mmu.c | 1 + 3 files changed, 50 insertions(+), 13 deletions(-) diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index 8fb6b4f1a5..4fffde961a 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -3,6 +3,9 @@ * * Copyright (c) 2009 Edgar E. Iglesias. * + * https://docs.amd.com/v/u/en-US/xps_intc + * DS572: LogiCORE IP XPS Interrupt Controller (v2.01a) + * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal * in the Software without restriction, including without limitation the r= ights @@ -49,6 +52,7 @@ struct XpsIntc { SysBusDevice parent_obj; =20 + bool little_endian_model; MemoryRegion mmio; qemu_irq parent_irq; =20 @@ -140,17 +144,39 @@ static void pic_write(void *opaque, hwaddr addr, update_irq(p); } =20 -static const MemoryRegionOps pic_ops =3D { - .read =3D pic_read, - .write =3D pic_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .impl =3D { - .min_access_size =3D 4, - .max_access_size =3D 4, +static const MemoryRegionOps pic_ops[2] =3D { + { + .read =3D pic_read, + .write =3D pic_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + /* + * All XPS INTC registers are accessed through the PLB interfa= ce. + * The base address for these registers is provided by the + * configuration parameter, C_BASEADDR. Each register is 32 bi= ts + * although some bits may be unused and is accessed on a 4-byte + * boundary offset from the base address. + */ + .min_access_size =3D 4, + .max_access_size =3D 4, + }, }, - .valid =3D { - .min_access_size =3D 4, - .max_access_size =3D 4 + { + .read =3D pic_read, + .write =3D pic_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, } }; =20 @@ -174,13 +200,21 @@ static void xilinx_intc_init(Object *obj) =20 qdev_init_gpio_in(DEVICE(obj), irq_handler, 32); sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq); - - memory_region_init_io(&p->mmio, obj, &pic_ops, p, "xlnx.xps-intc", - R_MAX * 4); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio); } =20 +static void xilinx_intc_realize(DeviceState *dev, Error **errp) +{ + XpsIntc *p =3D XILINX_INTC(dev); + + memory_region_init_io(&p->mmio, OBJECT(dev), + &pic_ops[p->little_endian_model], + p, "xlnx.xps-intc", + R_MAX * 4); +} + static Property xilinx_intc_properties[] =3D { + DEFINE_PROP_BOOL("little-endian", XpsIntc, little_endian_model, true), DEFINE_PROP_UINT32("kind-of-intr", XpsIntc, c_kind_of_intr, 0), DEFINE_PROP_END_OF_LIST(), }; @@ -189,6 +223,7 @@ static void xilinx_intc_class_init(ObjectClass *klass, = void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 + dc->realize =3D xilinx_intc_realize; device_class_set_props(dc, xilinx_intc_properties); } =20 diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_= ml605_mmu.c index d2b2109065..64e8cadbee 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -111,6 +111,7 @@ petalogix_ml605_init(MachineState *machine) =20 =20 dev =3D qdev_new("xlnx.xps-intc"); + qdev_prop_set_bit(dev, "little-endian", true); qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petal= ogix_s3adsp1800_mmu.c index 8110be8371..af949196d3 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -95,6 +95,7 @@ petalogix_s3adsp1800_init(MachineState *machine) 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); =20 dev =3D qdev_new("xlnx.xps-intc"); + qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); qdev_prop_set_uint32(dev, "kind-of-intr", 1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); --=20 2.45.2 From nobody Sat Nov 23 21:43:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.libvirt.org designates 8.43.85.245 as permitted sender) client-ip=8.43.85.245; envelope-from=devel-bounces@lists.libvirt.org; helo=lists.libvirt.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of lists.libvirt.org designates 8.43.85.245 as permitted sender) smtp.mailfrom=devel-bounces@lists.libvirt.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.libvirt.org (lists.libvirt.org [8.43.85.245]) by mx.zohomail.com with SMTPS id 1730942684962992.6909296321785; Wed, 6 Nov 2024 17:24:44 -0800 (PST) Received: by lists.libvirt.org (Postfix, from userid 996) id D5EE11548; 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AJvYcCWX6/QWIb46MjGlF7YeURRjGV9SWNhx/mTbXgfUIOXstxqtZuJJ0NBv5eg1j5fGYCJQnP/wSw==@lists.libvirt.org X-Gm-Message-State: AOJu0Yw1TzUKzLz9XJ/pjd3+xvsPkIulGGKJzHFVZtUWMYLS5prSwbJ5 49ZeAKmmVwb9keDaVbighms+vooy5Pu83AJ2+B2CFiJLKWLyx+3i5L67ZqTD3rs= X-Google-Smtp-Source: AGHT+IFmvuDn80/qJZJ0/3+MGoYVqXc9lTQbgEvElc+t8ldwX/W7PeKqgXuxIlWkYJlDfusLVItldw== X-Received: by 2002:a05:6000:71a:b0:37d:4e03:ff8e with SMTP id ffacd0b85a97d-381edaed24cmr211383f8f.28.1730942571912; Wed, 06 Nov 2024 17:22:51 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Anton Johansson , qemu-devel@nongnu.org Subject: [RFC PATCH v2 04/16] hw/net/xilinx_ethlite: Simplify by having configurable endianness Date: Thu, 7 Nov 2024 01:22:10 +0000 Message-ID: <20241107012223.94337-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107012223.94337-1-philmd@linaro.org> References: <20241107012223.94337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-ID-Hash: MKDBFJAHRJRS4XJJV4SAHXHA35FTZQQW X-Message-ID-Hash: MKDBFJAHRJRS4XJJV4SAHXHA35FTZQQW X-MailFrom: philmd@linaro.org X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-config-1; header-match-config-2; header-match-config-3; header-match-devel.lists.libvirt.org-0 CC: Paolo Bonzini , Thomas Huth , Jason Wang , devel@lists.libvirt.org, qemu-ppc@nongnu.org, Alistair Francis , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , "Edgar E. Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= X-Mailman-Version: 3.2.2 Precedence: list List-Id: Development discussions about the libvirt library & tools Archived-At: List-Archive: List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1730942686611116600 Content-Type: text/plain; charset="utf-8" The Xilinx 'ethlite' device was added in commit b43848a100 ("xilinx: Add ethlite emulation"), being only built back then for a big-endian MicroBlaze target (see commit 72b675caac "microblaze: Hook into the build-system"). I/O endianness access was then clarified in commit d48751ed4f ("xilinx-ethlite: Simplify byteswapping to/from brams"). Here the 'fix' was to use tswap32(). Since the machine was built as big-endian target, tswap32() use means the fix was for a little endian host. While the datasheet (reference added in file header) is not precise about it, we interpret such change as the device expects accesses in big-endian order. Instead of having a double swapping, one in the core memory layer due to DEVICE_NATIVE_ENDIAN and a second one with the tswap calls, allow the machine code to select the proper endianness desired, removing the need of tswap(). Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness on the single machine using the device. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- RFC until I digest Paolo's review from v1: https://lore.kernel.org/qemu-devel/34f6fe2f-06e0-4e2a-a361-2d662f6814b5@red= hat.com/ --- hw/microblaze/petalogix_s3adsp1800_mmu.c | 2 + hw/net/xilinx_ethlite.c | 54 +++++++++++++++++------- 2 files changed, 40 insertions(+), 16 deletions(-) diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petal= ogix_s3adsp1800_mmu.c index af949196d3..f2e2dc2fd7 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -121,9 +121,11 @@ petalogix_s3adsp1800_init(MachineState *machine) sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); =20 dev =3D qdev_new("xlnx.xps-ethernetlite"); + qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); qemu_configure_nic_device(dev, true, NULL); qdev_prop_set_uint32(dev, "tx-ping-pong", 0); qdev_prop_set_uint32(dev, "rx-ping-pong", 0); + qdev_prop_set_bit(dev, "little-endian-model", !TARGET_BIG_ENDIAN); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]); diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index e84b4cdd35..d2e7939569 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -3,6 +3,9 @@ * * Copyright (c) 2009 Edgar E. Iglesias. * + * DS580: https://docs.amd.com/v/u/en-US/xps_ethernetlite + * LogiCORE IP XPS Ethernet Lite Media Access Controller + * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal * in the Software without restriction, including without limitation the r= ights @@ -25,7 +28,6 @@ #include "qemu/osdep.h" #include "qemu/module.h" #include "qom/object.h" -#include "exec/tswap.h" #include "hw/sysbus.h" #include "hw/irq.h" #include "hw/qdev-properties.h" @@ -60,6 +62,7 @@ struct xlx_ethlite { SysBusDevice parent_obj; =20 + bool little_endian_model; MemoryRegion mmio; qemu_irq irq; NICState *nic; @@ -103,9 +106,10 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) break; =20 default: - r =3D tswap32(s->regs[addr]); + r =3D s->regs[addr]; break; } + return r; } =20 @@ -161,22 +165,37 @@ eth_write(void *opaque, hwaddr addr, break; =20 default: - s->regs[addr] =3D tswap32(value); + s->regs[addr] =3D value; break; } } =20 -static const MemoryRegionOps eth_ops =3D { - .read =3D eth_read, - .write =3D eth_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .impl =3D { - .min_access_size =3D 4, - .max_access_size =3D 4, +static const MemoryRegionOps eth_ops[2] =3D { + { + .read =3D eth_read, + .write =3D eth_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, }, - .valid =3D { - .min_access_size =3D 4, - .max_access_size =3D 4 + { + .read =3D eth_read, + .write =3D eth_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, } }; =20 @@ -237,6 +256,10 @@ static void xilinx_ethlite_realize(DeviceState *dev, E= rror **errp) { struct xlx_ethlite *s =3D XILINX_ETHLITE(dev); =20 + memory_region_init_io(&s->mmio, OBJECT(dev), + ð_ops[s->little_endian_model], s, + "xlnx.xps-ethernetlite", R_MAX * 4); + qemu_macaddr_default_if_unset(&s->conf.macaddr); s->nic =3D qemu_new_nic(&net_xilinx_ethlite_info, &s->conf, object_get_typename(OBJECT(dev)), dev->id, @@ -249,13 +272,12 @@ static void xilinx_ethlite_init(Object *obj) struct xlx_ethlite *s =3D XILINX_ETHLITE(obj); =20 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); - - memory_region_init_io(&s->mmio, obj, ð_ops, s, - "xlnx.xps-ethernetlite", R_MAX * 4); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); } =20 static Property xilinx_ethlite_properties[] =3D { + DEFINE_PROP_BOOL("little-endian", struct xlx_ethlite, + little_endian_model, true), DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, = 1), DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, = 1), DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf), --=20 2.45.2 From nobody Sat Nov 23 21:43:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Edgar E . Iglesias" Subject: [RFC PATCH v2 05/16] hw/timer/xilinx_timer: Allow down to 8-bit memory access Date: Thu, 7 Nov 2024 01:22:11 +0000 Message-ID: <20241107012223.94337-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107012223.94337-1-philmd@linaro.org> References: <20241107012223.94337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730942610486116600 Allow down to 8-bit access, per the datasheet (reference added in previous commit): "Timer Counter registers are accessed as one of the following types: =E2=80=A2 Byte (8 bits) =E2=80=A2 Half word (2 bytes) =E2=80=A2 Word (4 bytes)" Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Acked-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- RFC: This breaks the UART qtest, instead of having TX register receiving 'T' =3D 0x54, it receives 0x54000000, converted to '\0' char. It works if we use SWI instead of SBI (storing 32-bit). --- hw/timer/xilinx_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index 383fc8b3c8..c117bff225 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -198,7 +198,7 @@ static const MemoryRegionOps timer_ops =3D { .max_access_size =3D 4, }, .valid =3D { - .min_access_size =3D 4, + .min_access_size =3D 1, .max_access_size =3D 4 } }; --=20 2.45.2 From nobody Sat Nov 23 21:43:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1730942653; cv=none; d=zohomail.com; s=zohoarc; b=nCqrRGKDs6gKCOjiGWqE/nG8beonrVGwssPYRYGGEQc2O50wcu2OVhASCoGDas8EO+N7I7adSXcwCCLeEGzP0pCmNucNekVEngz+AzQDc+PMPRmbGPFniQ5YRDcZ5OjRu2bDhrf7rnCq7DPbaiaympoRjSuWcf/Cf3U7ApQbZ9U= ARC-Message-Signature: i=1; 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Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 06/16] hw/timer/xilinx_timer: Make device endianness configurable Date: Thu, 7 Nov 2024 01:22:12 +0000 Message-ID: <20241107012223.94337-7-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107012223.94337-1-philmd@linaro.org> References: <20241107012223.94337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730942654640116600 Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness for each machine using the device. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/microblaze/petalogix_ml605_mmu.c | 1 + hw/microblaze/petalogix_s3adsp1800_mmu.c | 1 + hw/ppc/virtex_ml507.c | 1 + hw/timer/xilinx_timer.c | 46 +++++++++++++++++------- 4 files changed, 36 insertions(+), 13 deletions(-) diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_= ml605_mmu.c index 64e8cadbee..f4ec983fee 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -127,6 +127,7 @@ petalogix_ml605_init(MachineState *machine) =20 /* 2 timers at irq 2 @ 100 Mhz. */ dev =3D qdev_new("xlnx.xps-timer"); + qdev_prop_set_bit(dev, "little-endian", true); qdev_prop_set_uint32(dev, "one-timer-only", 0); qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petal= ogix_s3adsp1800_mmu.c index f2e2dc2fd7..c0136d84c3 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -114,6 +114,7 @@ petalogix_s3adsp1800_init(MachineState *machine) =20 /* 2 timers at irq 2 @ 62 Mhz. */ dev =3D qdev_new("xlnx.xps-timer"); + qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); qdev_prop_set_uint32(dev, "one-timer-only", 0); qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index f378e5c4a9..ea0b3a56fe 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -230,6 +230,7 @@ static void virtex_init(MachineState *machine) =20 /* 2 timers at irq 2 @ 62 Mhz. */ dev =3D qdev_new("xlnx.xps-timer"); + qdev_prop_set_bit(dev, "little-endian", false); qdev_prop_set_uint32(dev, "one-timer-only", 0); qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index c117bff225..d356807d7c 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -3,6 +3,9 @@ * * Copyright (c) 2009 Edgar E. Iglesias. * + * DS573: https://docs.amd.com/v/u/en-US/xps_timer + * LogiCORE IP XPS Timer/Counter (v1.02a) + * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal * in the Software without restriction, including without limitation the r= ights @@ -69,6 +72,7 @@ struct XpsTimerState { SysBusDevice parent_obj; =20 + bool little_endian_model; MemoryRegion mmio; qemu_irq irq; uint8_t one_timer_only; @@ -189,17 +193,31 @@ timer_write(void *opaque, hwaddr addr, timer_update_irq(t); } =20 -static const MemoryRegionOps timer_ops =3D { - .read =3D timer_read, - .write =3D timer_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .impl =3D { - .min_access_size =3D 4, - .max_access_size =3D 4, - }, - .valid =3D { - .min_access_size =3D 1, - .max_access_size =3D 4 +static const MemoryRegionOps timer_ops[2] =3D { + { + .read =3D timer_read, + .write =3D timer_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, + }, { + .read =3D timer_read, + .write =3D timer_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, } }; =20 @@ -233,8 +251,9 @@ static void xilinx_timer_realize(DeviceState *dev, Erro= r **errp) ptimer_transaction_commit(xt->ptimer); } =20 - memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, "xlnx.xps-ti= mer", - R_MAX * 4 * num_timers(t)); + memory_region_init_io(&t->mmio, OBJECT(t), + &timer_ops[t->little_endian_model], t, + "xlnx.xps-timer", R_MAX * 4 * num_timers(t)); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->mmio); } =20 @@ -247,6 +266,7 @@ static void xilinx_timer_init(Object *obj) } =20 static Property xilinx_timer_properties[] =3D { + DEFINE_PROP_BOOL("little-endian", XpsTimerState, little_endian_model, = true), DEFINE_PROP_UINT32("clock-frequency", XpsTimerState, freq_hz, 62 * 100= 0000), DEFINE_PROP_UINT8("one-timer-only", XpsTimerState, one_timer_only, 0), DEFINE_PROP_END_OF_LIST(), --=20 2.45.2 From nobody Sat Nov 23 21:43:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 07/16] hw/char/xilinx_uartlite: Make device endianness configurable Date: Thu, 7 Nov 2024 01:22:13 +0000 Message-ID: <20241107012223.94337-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107012223.94337-1-philmd@linaro.org> References: <20241107012223.94337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730942754869116601 Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness on the single machine using the device. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/char/xilinx_uartlite.c | 44 ++++++++++++++++-------- hw/microblaze/petalogix_s3adsp1800_mmu.c | 1 + 2 files changed, 31 insertions(+), 14 deletions(-) diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c index 3022b3d8ef..c43bf1a030 100644 --- a/hw/char/xilinx_uartlite.c +++ b/hw/char/xilinx_uartlite.c @@ -57,6 +57,7 @@ struct XilinxUARTLite { SysBusDevice parent_obj; =20 + bool little_endian_model; MemoryRegion mmio; CharBackend chr; qemu_irq irq; @@ -166,21 +167,36 @@ uart_write(void *opaque, hwaddr addr, uart_update_irq(s); } =20 -static const MemoryRegionOps uart_ops =3D { - .read =3D uart_read, - .write =3D uart_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .impl =3D { - .min_access_size =3D 4, - .max_access_size =3D 4, - }, - .valid =3D { - .min_access_size =3D 1, - .max_access_size =3D 4 +static const MemoryRegionOps uart_ops[2] =3D { + { + .read =3D uart_read, + .write =3D uart_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, + }, { + .read =3D uart_read, + .write =3D uart_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, } }; =20 static Property xilinx_uartlite_properties[] =3D { + DEFINE_PROP_BOOL("little-endian", XilinxUARTLite, little_endian_model,= true), DEFINE_PROP_CHR("chardev", XilinxUARTLite, chr), DEFINE_PROP_END_OF_LIST(), }; @@ -219,6 +235,9 @@ static void xilinx_uartlite_realize(DeviceState *dev, E= rror **errp) { XilinxUARTLite *s =3D XILINX_UARTLITE(dev); =20 + memory_region_init_io(&s->mmio, OBJECT(dev), + &uart_ops[s->little_endian_model], + s, "xlnx.xps-uartlite", R_MAX * 4); qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, NULL, s, NULL, true); } @@ -228,9 +247,6 @@ static void xilinx_uartlite_init(Object *obj) XilinxUARTLite *s =3D XILINX_UARTLITE(obj); =20 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); - - memory_region_init_io(&s->mmio, obj, &uart_ops, s, - "xlnx.xps-uartlite", R_MAX * 4); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); } =20 diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petal= ogix_s3adsp1800_mmu.c index c0136d84c3..bd8b85fa54 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -107,6 +107,7 @@ petalogix_s3adsp1800_init(MachineState *machine) } =20 dev =3D qdev_new(TYPE_XILINX_UARTLITE); + qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); qdev_prop_set_chr(dev, "chardev", serial_hd(0)); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR); --=20 2.45.2 From nobody Sat Nov 23 21:43:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1730942657; cv=none; d=zohomail.com; s=zohoarc; b=Y/4/Vvn+uHADEopepTu3iCFeidfxfveYM+FJeHVgYt2AG1e2ploni+GYHsuTRREEASAqeNapbihf8udEDslZtXDoHlO3roSq0plodGqB6x4389BqMPp770ObDivi2u5JIWCH9ed9hAyA8sPTeNE+O7PUtYQfFowMxzEO9WNm6o4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730942657; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 06 Nov 2024 17:23:16 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Anton Johansson , qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Jason Wang , devel@lists.libvirt.org, qemu-ppc@nongnu.org, Alistair Francis , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , "Edgar E. Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 08/16] hw/ssi/xilinx_spi: Make device endianness configurable Date: Thu, 7 Nov 2024 01:22:14 +0000 Message-ID: <20241107012223.94337-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107012223.94337-1-philmd@linaro.org> References: <20241107012223.94337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730942658623116600 Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness on the single machine using the device. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/arm/xlnx-zynqmp.c | 4 ++++ hw/ssi/xilinx_spi.c | 29 +++++++++++++++++++++-------- 2 files changed, 25 insertions(+), 8 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index ab2d50e31b..e735dbdf82 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -714,6 +714,10 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Erro= r **errp) for (i =3D 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { gchar *bus_name; =20 + if (!object_property_set_bool(OBJECT(&s->spi[i])), "little-endian", + true, errp)) { + return; + } if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { return; } diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c index 7f1e1808c5..2a0c9bca05 100644 --- a/hw/ssi/xilinx_spi.c +++ b/hw/ssi/xilinx_spi.c @@ -83,6 +83,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XilinxSPI, XILINX_SPI) struct XilinxSPI { SysBusDevice parent_obj; =20 + bool little_endian_model; MemoryRegion mmio; =20 qemu_irq irq; @@ -313,13 +314,23 @@ done: xlx_spi_update_irq(s); } =20 -static const MemoryRegionOps spi_ops =3D { - .read =3D spi_read, - .write =3D spi_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .valid =3D { - .min_access_size =3D 4, - .max_access_size =3D 4 +static const MemoryRegionOps spi_ops[2] =3D { + { + .read =3D spi_read, + .write =3D spi_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + }, { + .read =3D spi_read, + .write =3D spi_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, } }; =20 @@ -339,7 +350,8 @@ static void xilinx_spi_realize(DeviceState *dev, Error = **errp) sysbus_init_irq(sbd, &s->cs_lines[i]); } =20 - memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s, + memory_region_init_io(&s->mmio, OBJECT(s), + &spi_ops[s->little_endian_model], s, "xilinx-spi", R_MAX * 4); sysbus_init_mmio(sbd, &s->mmio); =20 @@ -362,6 +374,7 @@ static const VMStateDescription vmstate_xilinx_spi =3D { }; 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Wed, 06 Nov 2024 17:23:23 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Anton Johansson , qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Jason Wang , devel@lists.libvirt.org, qemu-ppc@nongnu.org, Alistair Francis , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , "Edgar E. Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 09/16] hw/ssi/xilinx_spips: Make device endianness configurable Date: Thu, 7 Nov 2024 01:22:15 +0000 Message-ID: <20241107012223.94337-10-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107012223.94337-1-philmd@linaro.org> References: <20241107012223.94337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730942746982116600 Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness on the single machine using the device. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/ssi/xilinx_spips.h | 1 + hw/arm/xilinx_zynq.c | 1 + hw/ssi/xilinx_spips.c | 46 ++++++++++++++++++++++++++--------- 3 files changed, 36 insertions(+), 12 deletions(-) diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 7a754bf67a..451c3758b3 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -101,6 +101,7 @@ typedef struct XilinxQSPIPS XilinxQSPIPS; struct XlnxZynqMPQSPIPS { XilinxQSPIPS parent_obj; =20 + bool little_endian_model; StreamSink *dma; int gqspi_irqline; =20 diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index fde4d946b7..bcc0022c17 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -142,6 +142,7 @@ static inline int zynq_init_spi_flashes(uint32_t base_a= ddr, qemu_irq irq, int num_ss =3D is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; =20 dev =3D qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); + qdev_prop_set_bit(dev, "little-endian", true); qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); qdev_prop_set_uint8(dev, "num-busses", num_busses); diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index aeb462c3ce..5c6f0dd079 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -1251,17 +1251,32 @@ static MemTxResult lqspi_write(void *opaque, hwaddr= offset, uint64_t value, return MEMTX_ERROR; } =20 -static const MemoryRegionOps lqspi_ops =3D { - .read_with_attrs =3D lqspi_read, - .write_with_attrs =3D lqspi_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .impl =3D { - .min_access_size =3D 4, - .max_access_size =3D 4, +static const MemoryRegionOps lqspi_ops[2] =3D { + { + .read_with_attrs =3D lqspi_read, + .write_with_attrs =3D lqspi_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4 + }, }, - .valid =3D { - .min_access_size =3D 1, - .max_access_size =3D 4 + { + .read_with_attrs =3D lqspi_read, + .write_with_attrs =3D lqspi_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, } }; =20 @@ -1325,8 +1340,9 @@ static void xilinx_qspips_realize(DeviceState *dev, E= rror **errp) s->num_txrx_bytes =3D 4; =20 xilinx_spips_realize(dev, errp); - memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi", - (1 << LQSPI_ADDRESS_BITS) * 2); + memory_region_init_io(&s->mmlqspi, OBJECT(s), + &lqspi_ops[s->little_endian_model], + s, "lqspi", (1 << LQSPI_ADDRESS_BITS) * 2); sysbus_init_mmio(sbd, &s->mmlqspi); =20 q->lqspi_cached_addr =3D ~0ULL; @@ -1432,12 +1448,18 @@ static Property xilinx_spips_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static Property xilinx_qspips_properties[] =3D { + DEFINE_PROP_BOOL("little-endian", XilinxQSPIPS, little_endian_model, t= rue), + DEFINE_PROP_END_OF_LIST(), +}; + static void xilinx_qspips_class_init(ObjectClass *klass, void * data) { DeviceClass *dc =3D DEVICE_CLASS(klass); XilinxSPIPSClass *xsc =3D XILINX_SPIPS_CLASS(klass); =20 dc->realize =3D xilinx_qspips_realize; + device_class_set_props(dc, xilinx_qspips_properties); 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Wed, 06 Nov 2024 17:23:30 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Anton Johansson , qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Jason Wang , devel@lists.libvirt.org, qemu-ppc@nongnu.org, Alistair Francis , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , "Edgar E. Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PATCH v2 10/16] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx Date: Thu, 7 Nov 2024 01:22:16 +0000 Message-ID: <20241107012223.94337-11-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107012223.94337-1-philmd@linaro.org> References: <20241107012223.94337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730942763113116600 Extract the implicit MO_TE definition in order to replace it by runtime variable in the next commit. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/microblaze); \ done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/microblaze/translate.c | 36 +++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 4beaf69e76..4c25b1e438 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -779,13 +779,13 @@ static bool trans_lbui(DisasContext *dc, arg_typeb *a= rg) static bool trans_lhu(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } =20 static bool trans_lhur(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); } =20 static bool trans_lhuea(DisasContext *dc, arg_typea *arg) @@ -797,26 +797,26 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *= arg) return true; #else TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); #endif } =20 static bool trans_lhui(DisasContext *dc, arg_typeb *arg) { TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } =20 static bool trans_lw(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } =20 static bool trans_lwr(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); } =20 static bool trans_lwea(DisasContext *dc, arg_typea *arg) @@ -828,14 +828,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *a= rg) return true; #else TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); #endif } =20 static bool trans_lwi(DisasContext *dc, arg_typeb *arg) { TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } =20 static bool trans_lwx(DisasContext *dc, arg_typea *arg) @@ -845,7 +845,7 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); =20 - tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); + tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL); tcg_gen_mov_tl(cpu_res_addr, addr); =20 if (arg->rd) { @@ -929,13 +929,13 @@ static bool trans_sbi(DisasContext *dc, arg_typeb *ar= g) static bool trans_sh(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false= ); } =20 static bool trans_shr(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); } =20 static bool trans_shea(DisasContext *dc, arg_typea *arg) @@ -947,26 +947,26 @@ static bool trans_shea(DisasContext *dc, arg_typea *a= rg) return true; #else TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false= ); #endif } =20 static bool trans_shi(DisasContext *dc, arg_typeb *arg) { TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false= ); } =20 static bool trans_sw(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false= ); } =20 static bool trans_swr(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); } =20 static bool trans_swea(DisasContext *dc, arg_typea *arg) @@ -978,14 +978,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *a= rg) return true; #else TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false= ); #endif } =20 static bool trans_swi(DisasContext *dc, arg_typeb *arg) { TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false= ); } =20 static bool trans_swx(DisasContext *dc, arg_typea *arg) @@ -1014,7 +1014,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *ar= g) =20 tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val, reg_for_write(dc, arg->rd), - dc->mem_index, MO_TEUL); + dc->mem_index, MO_TE | MO_UL); =20 tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail); =20 --=20 2.45.2 From nobody Sat Nov 23 21:43:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 11/16] target/microblaze: Set MO_TE once in do_load() / do_store() Date: Thu, 7 Nov 2024 01:22:17 +0000 Message-ID: <20241107012223.94337-12-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107012223.94337-1-philmd@linaro.org> References: <20241107012223.94337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730942726993116600 All callers of do_load() / do_store() set MO_TE flag. Set it once in the callees. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/microblaze/translate.c | 36 +++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 4c25b1e438..86f3c19618 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -712,6 +712,8 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr= , MemOp mop, { MemOp size =3D mop & MO_SIZE; =20 + mop |=3D MO_TE; + /* * When doing reverse accesses we need to do two things. * @@ -779,13 +781,13 @@ static bool trans_lbui(DisasContext *dc, arg_typeb *a= rg) static bool trans_lhu(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } =20 static bool trans_lhur(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, true); } =20 static bool trans_lhuea(DisasContext *dc, arg_typea *arg) @@ -797,26 +799,26 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *= arg) return true; #else TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false); #endif } =20 static bool trans_lhui(DisasContext *dc, arg_typeb *arg) { TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } =20 static bool trans_lw(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } =20 static bool trans_lwr(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, true); } =20 static bool trans_lwea(DisasContext *dc, arg_typea *arg) @@ -828,14 +830,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *a= rg) return true; #else TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false); #endif } =20 static bool trans_lwi(DisasContext *dc, arg_typeb *arg) { TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } =20 static bool trans_lwx(DisasContext *dc, arg_typea *arg) @@ -862,6 +864,8 @@ static bool do_store(DisasContext *dc, int rd, TCGv add= r, MemOp mop, { MemOp size =3D mop & MO_SIZE; =20 + mop |=3D MO_TE; + /* * When doing reverse accesses we need to do two things. * @@ -929,13 +933,13 @@ static bool trans_sbi(DisasContext *dc, arg_typeb *ar= g) static bool trans_sh(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false= ); + return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } =20 static bool trans_shr(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, true); } =20 static bool trans_shea(DisasContext *dc, arg_typea *arg) @@ -947,26 +951,26 @@ static bool trans_shea(DisasContext *dc, arg_typea *a= rg) return true; #else TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false= ); + return do_store(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false); #endif } =20 static bool trans_shi(DisasContext *dc, arg_typeb *arg) { TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false= ); + return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } =20 static bool trans_sw(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false= ); + return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } =20 static bool trans_swr(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, true); } =20 static bool trans_swea(DisasContext *dc, arg_typea *arg) @@ -978,14 +982,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *a= rg) return true; #else TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false= ); + return do_store(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false); #endif } =20 static bool trans_swi(DisasContext *dc, arg_typeb *arg) { TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false= ); + return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } =20 static bool trans_swx(DisasContext *dc, arg_typea *arg) --=20 2.45.2 From nobody Sat Nov 23 21:43:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1730942747; cv=none; d=zohomail.com; s=zohoarc; b=jIT1FYzz/QXQ4h5c5zTsGWIKK7LDAzUhkCVY405rqvc0YscZ+Atrr7so2iEIpWB4bT0gGydWSHL/cZAKP3xGjnMkz5ibkZh7OS3bkbQE/KCSDeQpT1vvXk/4VG9niYM5QdKYQKZyAfyi5gQShVHzMblqUc/TTs+yk2o9jCgMDIM= ARC-Message-Signature: i=1; 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Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 12/16] target/microblaze: Introduce mo_endian() helper Date: Thu, 7 Nov 2024 01:22:18 +0000 Message-ID: <20241107012223.94337-13-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107012223.94337-1-philmd@linaro.org> References: <20241107012223.94337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730942748938116600 mo_endian() returns the target endianness, currently static. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/microblaze/translate.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 86f3c19618..0b466db694 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -707,12 +707,17 @@ static void record_unaligned_ess(DisasContext *dc, in= t rd, } #endif =20 +static inline MemOp mo_endian(DisasContext *dc) +{ + return MO_TE; +} + static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, int mem_index, bool rev) { MemOp size =3D mop & MO_SIZE; =20 - mop |=3D MO_TE; + mop |=3D mo_endian(dc); =20 /* * When doing reverse accesses we need to do two things. @@ -847,7 +852,8 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); =20 - tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL); + tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, + mo_endian(dc) | MO_UL); tcg_gen_mov_tl(cpu_res_addr, addr); =20 if (arg->rd) { @@ -864,7 +870,7 @@ static bool do_store(DisasContext *dc, int rd, TCGv add= r, MemOp mop, { MemOp size =3D mop & MO_SIZE; =20 - mop |=3D MO_TE; + mop |=3D mo_endian(dc); =20 /* * When doing reverse accesses we need to do two things. @@ -1018,7 +1024,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *ar= g) =20 tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val, reg_for_write(dc, arg->rd), - dc->mem_index, MO_TE | MO_UL); + dc->mem_index, mo_endian(dc) | MO_UL); =20 tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail); =20 --=20 2.45.2 From nobody Sat Nov 23 21:43:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 13/16] target/microblaze: Consider endianness while translating code Date: Thu, 7 Nov 2024 01:22:19 +0000 Message-ID: <20241107012223.94337-14-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107012223.94337-1-philmd@linaro.org> References: <20241107012223.94337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730942726834116600 Consider the CPU ENDI bit, swap instructions when the CPU endianness doesn't match the binary one. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/microblaze/cpu.h | 7 +++++++ target/microblaze/translate.c | 5 +++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 3e5a3e5c60..6d540713eb 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -412,6 +412,13 @@ void mb_tcg_init(void); /* Ensure there is no overlap between the two masks. */ QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); =20 +static inline bool mb_cpu_is_big_endian(CPUState *cs) +{ + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + + return !cpu->cfg.endi; +} + static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0b466db694..5595ae4fad 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -709,7 +709,7 @@ static void record_unaligned_ess(DisasContext *dc, int = rd, =20 static inline MemOp mo_endian(DisasContext *dc) { - return MO_TE; + return dc->cfg->endi ? MO_LE : MO_BE; } =20 static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, @@ -1646,7 +1646,8 @@ static void mb_tr_translate_insn(DisasContextBase *dc= b, CPUState *cs) =20 dc->tb_flags_to_set =3D 0; =20 - ir =3D translator_ldl(cpu_env(cs), &dc->base, dc->base.pc_next); + ir =3D translator_ldl_swap(cpu_env(cs), &dc->base, dc->base.pc_next, + mb_cpu_is_big_endian(cs) !=3D TARGET_BIG_ENDI= AN); if (!decode(dc, ir)) { trap_illegal(dc, true); } --=20 2.45.2 From nobody Sat Nov 23 21:43:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1730942750; cv=none; d=zohomail.com; s=zohoarc; b=gEf5mBCHjQ1UFfzTkLKLZBPW1J6ujYSuuLiJ18l3NGL+olMqsdvkq9bnIxcOuV3SIA0vcMI2Zg9P/RKU1ncuX5YW53KGfNJDn5jD25zJBv8OqsKzVS3gbPNeykNXU3MrhN+RK26c7YeZ63/OenGqSVSRkooMwKlSiUORRGZsrZs= ARC-Message-Signature: i=1; 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Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 14/16] hw/microblaze: Support various endianness for s3adsp1800 machines Date: Thu, 7 Nov 2024 01:22:20 +0000 Message-ID: <20241107012223.94337-15-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107012223.94337-1-philmd@linaro.org> References: <20241107012223.94337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730942751044116600 Introduce an abstract machine parent class which defines the 'little_endian' property. Duplicate the current machine, which endian is tied to the binary endianness, to one big endian and a little endian machine; updating the machine description. Keep the current default machine for each binary. 'petalogix-s3adsp1800' machine is aliased as: - 'petalogix-s3adsp1800-be' on big-endian binary, - 'petalogix-s3adsp1800-le' on little-endian one. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/microblaze/petalogix_s3adsp1800_mmu.c | 62 +++++++++++++++++++----- 1 file changed, 51 insertions(+), 11 deletions(-) diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petal= ogix_s3adsp1800_mmu.c index bd8b85fa54..533a833b41 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -55,8 +55,17 @@ #define ETHLITE_IRQ 1 #define UARTLITE_IRQ 3 =20 +typedef struct PetalogixS3adsp1800MachineClass { + MachineClass parent_obj; + + bool little_endian; +} PetalogixS3adsp1800MachineClass; + #define TYPE_PETALOGIX_S3ADSP1800_MACHINE \ - MACHINE_TYPE_NAME("petalogix-s3adsp1800") + MACHINE_TYPE_NAME("petalogix-s3adsp1800-common") +DECLARE_CLASS_CHECKERS(PetalogixS3adsp1800MachineClass, + PETALOGIX_S3ADSP1800_MACHINE, + TYPE_PETALOGIX_S3ADSP1800_MACHINE) =20 static void petalogix_s3adsp1800_init(MachineState *machine) @@ -71,11 +80,13 @@ petalogix_s3adsp1800_init(MachineState *machine) MemoryRegion *phys_ram =3D g_new(MemoryRegion, 1); qemu_irq irq[32]; MemoryRegion *sysmem =3D get_system_memory(); + PetalogixS3adsp1800MachineClass *pmc; =20 + pmc =3D PETALOGIX_S3ADSP1800_MACHINE_GET_CLASS(machine); cpu =3D MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); object_property_set_str(OBJECT(cpu), "version", "7.10.d", &error_abort= ); object_property_set_bool(OBJECT(cpu), "little-endian", - !TARGET_BIG_ENDIAN, &error_abort); + pmc->little_endian, &error_abort); qdev_realize(DEVICE(cpu), NULL, &error_abort); =20 /* Attach emulated BRAM through the LMB. */ @@ -95,7 +106,7 @@ petalogix_s3adsp1800_init(MachineState *machine) 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); =20 dev =3D qdev_new("xlnx.xps-intc"); - qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); + qdev_prop_set_bit(dev, "little-endian", pmc->little_endian); qdev_prop_set_uint32(dev, "kind-of-intr", 1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -107,7 +118,7 @@ petalogix_s3adsp1800_init(MachineState *machine) } =20 dev =3D qdev_new(TYPE_XILINX_UARTLITE); - qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); + qdev_prop_set_bit(dev, "little-endian", pmc->little_endian); qdev_prop_set_chr(dev, "chardev", serial_hd(0)); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR); @@ -115,7 +126,7 @@ petalogix_s3adsp1800_init(MachineState *machine) =20 /* 2 timers at irq 2 @ 62 Mhz. */ dev =3D qdev_new("xlnx.xps-timer"); - qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); + qdev_prop_set_bit(dev, "little-endian", pmc->little_endian); qdev_prop_set_uint32(dev, "one-timer-only", 0); qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -127,33 +138,62 @@ petalogix_s3adsp1800_init(MachineState *machine) qemu_configure_nic_device(dev, true, NULL); qdev_prop_set_uint32(dev, "tx-ping-pong", 0); qdev_prop_set_uint32(dev, "rx-ping-pong", 0); - qdev_prop_set_bit(dev, "little-endian-model", !TARGET_BIG_ENDIAN); + qdev_prop_set_bit(dev, "little-endian", pmc->little_endian); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]); =20 create_unimplemented_device("xps_gpio", GPIO_BASEADDR, 0x10000); =20 - microblaze_load_kernel(cpu, !TARGET_BIG_ENDIAN, ddr_base, ram_size, + microblaze_load_kernel(cpu, pmc->little_endian, ddr_base, ram_size, machine->initrd_filename, BINARY_DEVICE_TREE_FILE, NULL); } =20 -static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc, void = *data) +static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc, + bool little_endian) { MachineClass *mc =3D MACHINE_CLASS(oc); + PetalogixS3adsp1800MachineClass *pmc =3D PETALOGIX_S3ADSP1800_MACHINE_= CLASS(oc); =20 - mc->desc =3D "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800"; mc->init =3D petalogix_s3adsp1800_init; - mc->is_default =3D true; + pmc->little_endian =3D little_endian; + mc->desc =3D little_endian + ? "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800 (little = endian)" + : "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800 (big end= ian)"; + if (little_endian =3D=3D !TARGET_BIG_ENDIAN) { + mc->is_default =3D true; + mc->alias =3D "petalogix-s3adsp1800"; + } +} + +static void petalogix_s3adsp1800_machine_class_init_be(ObjectClass *oc, vo= id *data) +{ + petalogix_s3adsp1800_machine_class_init(oc, false); +} + +static void petalogix_s3adsp1800_machine_class_init_le(ObjectClass *oc, vo= id *data) +{ + petalogix_s3adsp1800_machine_class_init(oc, true); } =20 static const TypeInfo petalogix_s3adsp1800_machine_types[] =3D { { .name =3D TYPE_PETALOGIX_S3ADSP1800_MACHINE, .parent =3D TYPE_MACHINE, - .class_init =3D petalogix_s3adsp1800_machine_class_init, + .abstract =3D true, + .class_size =3D sizeof(PetalogixS3adsp1800MachineClass), + }, + { + .name =3D MACHINE_TYPE_NAME("petalogix-s3adsp1800-be"), + .parent =3D TYPE_PETALOGIX_S3ADSP1800_MACHINE, + .class_init =3D petalogix_s3adsp1800_machine_class_init_be, + }, + { + .name =3D MACHINE_TYPE_NAME("petalogix-s3adsp1800-le"), + .parent =3D TYPE_PETALOGIX_S3ADSP1800_MACHINE, + .class_init =3D petalogix_s3adsp1800_machine_class_init_le, }, }; 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Wed, 06 Nov 2024 17:24:00 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Anton Johansson , qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Jason Wang , devel@lists.libvirt.org, qemu-ppc@nongnu.org, Alistair Francis , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , "Edgar E. Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 15/16] tests/functional: Explicit endianness of microblaze assets Date: Thu, 7 Nov 2024 01:22:21 +0000 Message-ID: <20241107012223.94337-16-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107012223.94337-1-philmd@linaro.org> References: <20241107012223.94337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730942783052116600 The archive used in test_microblaze_s3adsp1800.py (testing a big-endian target) contains a big-endian kernel. Rename using the _BE suffix. Similarly, the archive in test_microblazeel_s3adsp1800 (testing a little-endian target) contains a little-endian kernel. Rename using _LE suffix. These changes will help when adding cross-endian kernel tests. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- tests/functional/test_microblaze_s3adsp1800.py | 6 +++--- tests/functional/test_microblazeel_s3adsp1800.py | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/functional/test_microblaze_s3adsp1800.py b/tests/functio= nal/test_microblaze_s3adsp1800.py index 4f692ffdb1..2b2f782270 100755 --- a/tests/functional/test_microblaze_s3adsp1800.py +++ b/tests/functional/test_microblaze_s3adsp1800.py @@ -17,14 +17,14 @@ class MicroblazeMachine(QemuSystemTest): =20 timeout =3D 90 =20 - ASSET_IMAGE =3D Asset( + ASSET_IMAGE_BE =3D Asset( ('https://qemu-advcal.gitlab.io/qac-best-of-multiarch/download/' 'day17.tar.xz'), '3ba7439dfbea7af4876662c97f8e1f0cdad9231fc166e4861d17042489270057') =20 - def test_microblaze_s3adsp1800(self): + def test_microblaze_s3adsp1800_be(self): self.set_machine('petalogix-s3adsp1800') - file_path =3D self.ASSET_IMAGE.fetch() + file_path =3D self.ASSET_IMAGE_BE.fetch() archive_extract(file_path, self.workdir) self.vm.set_console() self.vm.add_args('-kernel', self.workdir + '/day17/ballerina.bin') diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/funct= ional/test_microblazeel_s3adsp1800.py index faa3927f2e..1aee5149fb 100755 --- a/tests/functional/test_microblazeel_s3adsp1800.py +++ b/tests/functional/test_microblazeel_s3adsp1800.py @@ -17,14 +17,14 @@ class MicroblazeelMachine(QemuSystemTest): =20 timeout =3D 90 =20 - ASSET_IMAGE =3D Asset( + ASSET_IMAGE_LE =3D Asset( ('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'), 'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22') =20 - def test_microblazeel_s3adsp1800(self): + def test_microblazeel_s3adsp1800_le(self): self.require_netdev('user') self.set_machine('petalogix-s3adsp1800') - file_path =3D self.ASSET_IMAGE.fetch() + file_path =3D self.ASSET_IMAGE_LE.fetch() archive_extract(file_path, self.workdir) self.vm.set_console() self.vm.add_args('-kernel', self.workdir + '/day13/xmaton.bin') --=20 2.45.2 From nobody Sat Nov 23 21:43:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 06 Nov 2024 17:24:07 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Anton Johansson , qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Jason Wang , devel@lists.libvirt.org, qemu-ppc@nongnu.org, Alistair Francis , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , "Edgar E. Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 16/16] tests/functional: Add microblaze cross-endianness tests Date: Thu, 7 Nov 2024 01:22:22 +0000 Message-ID: <20241107012223.94337-17-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107012223.94337-1-philmd@linaro.org> References: <20241107012223.94337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730942668734116600 Copy/paste the current tests, but call the opposite endianness machines, testing: - petalogix-s3adsp1800-le machine (little-endian CPU) on the qemu-system-microblaze binary (big-endian) - petalogix-s3adsp1800-be machine (big-endian CPU) on the qemu-system-microblazeel binary (little-endian). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- .../functional/test_microblaze_s3adsp1800.py | 21 +++++++++++++++++++ .../test_microblazeel_s3adsp1800.py | 19 +++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/tests/functional/test_microblaze_s3adsp1800.py b/tests/functio= nal/test_microblaze_s3adsp1800.py index 2b2f782270..7f5e8b6024 100755 --- a/tests/functional/test_microblaze_s3adsp1800.py +++ b/tests/functional/test_microblaze_s3adsp1800.py @@ -36,5 +36,26 @@ def test_microblaze_s3adsp1800_be(self): # message, that's why we don't test for a later string here. This # needs some investigation by a microblaze wizard one day... =20 + ASSET_IMAGE_LE =3D Asset( + ('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'), + 'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22') + + def test_microblaze_s3adsp1800_le(self): + self.require_netdev('user') + self.set_machine('petalogix-s3adsp1800-le') + file_path =3D self.ASSET_IMAGE_LE.fetch() + archive_extract(file_path, self.workdir) + self.vm.set_console() + self.vm.add_args('-kernel', self.workdir + '/day13/xmaton.bin') + self.vm.add_args('-nic', 'user,tftp=3D' + self.workdir + '/day13/') + self.vm.launch() + wait_for_console_pattern(self, 'QEMU Advent Calendar 2023') + time.sleep(0.1) + exec_command(self, 'root') + time.sleep(0.1) + exec_command_and_wait_for_pattern(self, + 'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png', + '821cd3cab8efd16ad6ee5acc3642a8ea') + if __name__ =3D=3D '__main__': QemuSystemTest.main() diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/funct= ional/test_microblazeel_s3adsp1800.py index 1aee5149fb..60543009ba 100755 --- a/tests/functional/test_microblazeel_s3adsp1800.py +++ b/tests/functional/test_microblazeel_s3adsp1800.py @@ -38,5 +38,24 @@ def test_microblazeel_s3adsp1800_le(self): 'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png', '821cd3cab8efd16ad6ee5acc3642a8ea') =20 + ASSET_IMAGE_BE =3D Asset( + ('https://qemu-advcal.gitlab.io/qac-best-of-multiarch/download/' + 'day17.tar.xz'), + '3ba7439dfbea7af4876662c97f8e1f0cdad9231fc166e4861d17042489270057') + + def test_microblazeel_s3adsp1800_be(self): + self.set_machine('petalogix-s3adsp1800-be') + file_path =3D self.ASSET_IMAGE_BE.fetch() + archive_extract(file_path, self.workdir) + self.vm.set_console() + self.vm.add_args('-kernel', self.workdir + '/day17/ballerina.bin') + self.vm.launch() + wait_for_console_pattern(self, 'This architecture does not have ' + 'kernel memory protection') + # Note: + # The kernel sometimes gets stuck after the "This architecture ..." + # message, that's why we don't test for a later string here. This + # needs some investigation by a microblaze wizard one day... + if __name__ =3D=3D '__main__': QemuSystemTest.main() --=20 2.45.2