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([189.79.22.174]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-720bc2eb64esm11749765b3a.168.2024.11.06.05.34.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 05:34:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1730900082; x=1731504882; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vd7uhK27iZe8oGBrkgQRn9OqHPo3B4lI9DZBvvRNQAw=; b=ED6dm29JhmItjFuKV6GGt3d82psMLkklaDgjBkidusGR0UAG76JEdfVHRm9IZss2TC xeDN6V57nmqtymDp2vm19ZZ+fwc+dK2bQx8jyGv+gefgFUSlMoGlcmSVKGC3E/ho3uTr cKCx6h6Hjqa9GUOx2B/Pbu5odwaVz6b0rWO1AjaEo5OfWpQ6YwjfCDraxNxKC9w9pjNr aXONisjd4QQX3AICNOvq+aYQarO+WEWBmW1PushUI1XvhmfejzeiMLBBHhWQI0+wJpSH dtBKLjvCYUP63LXSwneOjQBnNzVu7v2jybtBTKiMhHbsS8Kre0/eLLIU+YHy5qj3MZYA XiqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730900082; x=1731504882; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vd7uhK27iZe8oGBrkgQRn9OqHPo3B4lI9DZBvvRNQAw=; b=GS1cXzGrXi5dy9nBkqjveL/5/kARGknHaBE/ExkhfogI12p0hgOjkIXMYc7JTVGQVM pCSP4MLh7Gi9C8zxS/Wst49sCksjJtgrB0jzhM7JBfRMxdOeyIn1VhWamJC0y2dUfoS2 wCM2GOTC1y+TNlovJV5FLyz2YGFvv8CM7/3acUkFnyjOzdpYWVfmkwFl1GVxNZjbsn6y SfiZjFK4+KhNojvEUowz5uaVCdzKzes7dhou/lzh/WSiqBRliHDmigl6/ThYZn0semef 3ifrmp+B5K2s513QZDL9lOKgj8a2duAHkYkMcPeskR3kC0NMUdIo90d7L0T+QsAIekpE XMiw== X-Gm-Message-State: AOJu0YwbV9OrIpwOl9Th5Cz1eOZsw7oTIGqhp0JN1VYFS99sBrVccBWF in72R8y7bShkOqigrGXbqToPdc9VFjsmyDRYaLaKw4gy0VjxqrMJuR5Ru1z3V1hM4lEA0Yzn2an e X-Google-Smtp-Source: AGHT+IEZKfSgSVAVgJgnMiXagw99BIg7rWlohlX9ZyOP82KF7HOyFN5o02dadtm82Nn9O2VsmgZWoA== X-Received: by 2002:a05:6a00:1303:b0:71e:4df3:b1d3 with SMTP id d2e1a72fcca58-72062f80b4cmr58116023b3a.4.1730900082498; Wed, 06 Nov 2024 05:34:42 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-10.0 7/7] docs/specs: add riscv-iommu-sys information Date: Wed, 6 Nov 2024 10:34:07 -0300 Message-ID: <20241106133407.604587-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241106133407.604587-1-dbarboza@ventanamicro.com> References: <20241106133407.604587-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1730900167207116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- docs/specs/riscv-iommu.rst | 30 +++++++++++++++++++++++++++--- docs/system/riscv/virt.rst | 10 ++++++++++ 2 files changed, 37 insertions(+), 3 deletions(-) diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.rst index 463f4cffb6..b1538c9ead 100644 --- a/docs/specs/riscv-iommu.rst +++ b/docs/specs/riscv-iommu.rst @@ -6,9 +6,9 @@ RISC-V IOMMU support for RISC-V machines QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec version 1.0 `iommu1.0`_. =20 -The emulation includes a PCI reference device, riscv-iommu-pci, that QEMU -RISC-V boards can use. The 'virt' RISC-V machine is compatible with this -device. +The emulation includes a PCI reference device (riscv-iommu-pci) and a plat= form +bus device (riscv-iommu-sys) that QEMU RISC-V boards can use. The 'virt' +RISC-V machine is compatible with both devices. =20 riscv-iommu-pci reference device -------------------------------- @@ -83,6 +83,30 @@ Several options are available to control the capabilitie= s of the device, namely: - "s-stage": enable s-stage support - "g-stage": enable g-stage support =20 +riscv-iommu-sys device +---------------------- + +This device implements the RISC-V IOMMU emulation as a platform bus device= that +RISC-V boards can use. + +For the 'virt' board the device is disabled by default. To enable it use = the +'iommu-sys' machine option: + +.. code-block:: bash + + $ qemu-system-riscv64 -M virt,iommu-sys=3Don (...) + +There is no options to configure the capabilities of this device in the 'v= irt' +board using the QEMU command line. The device is configured with the foll= owing +riscv-iommu options: + +- "ioatc-limit": default value (2Mb) +- "intremap": enabled +- "ats": enabled +- "off": on (DMA disabled) +- "s-stage": enabled +- "g-stage": enabled + .. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/downlo= ad/v1.0/riscv-iommu.pdf =20 .. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tje= znach@rivosinc.com/ diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst index 8e9a2e4dda..537aac0340 100644 --- a/docs/system/riscv/virt.rst +++ b/docs/system/riscv/virt.rst @@ -94,6 +94,12 @@ command line: =20 $ qemu-system-riscv64 -M virt -device riscv-iommu-pci (...) =20 +It also has support for the riscv-iommu-sys platform device: + +.. code-block:: bash + + $ qemu-system-riscv64 -M virt,iommu-sys=3Don (...) + Refer to :ref:`riscv-iommu` for more information on how the RISC-V IOMMU s= upport works. =20 @@ -129,6 +135,10 @@ The following machine-specific options are supported: having AIA IMSIC (i.e. "aia=3Daplic-imsic" selected). When not specified, the default number of per-HART VS-level AIA IMSIC pages is 0. =20 +- iommu-sys=3D[on|off] + + Enables the riscv-iommu-sys platform device. Defaults to 'off'. + Running Linux kernel -------------------- =20 --=20 2.45.2