From nobody Sat Nov 23 20:24:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1730900220; cv=none; d=zohomail.com; s=zohoarc; b=MELZCNx60OesEh9+uJU5W/VtK+40TzgqdQNpBhTaO/i8LytvSV42U7v2B/s8RsDVi2T7muZOJrAsfS6HQGTFm35VYCqOk0+Nouo4zoSXyWUKyAl7tNFMxfThjilgK6PAKXJJ2xiXnYxDpzgwY4p6VU2utDDRgMtswqN9lX33Opw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730900220; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DV1MjcpJEaxpGdQy9Gd1H5P1SEK291KM48+bJCTEyMY=; b=V7x+3rA4mab1VLCfA6r0+5r8POHAfY1ViQugeE8pficlSqRr6OXh+Xw6NyAxWGPAhNFdyIr5c/12NPLml2EAyhyhEy1y2zHKztrQEVSvUzIa0p/D6ACRqjTBTmsmaRJvkGP7Bev9NjUJEfbx2wto15bPdyU1u7DynR/E24dFPgw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1730900220167517.6580724271414; Wed, 6 Nov 2024 05:37:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t8gB4-0001fk-1E; Wed, 06 Nov 2024 08:34:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t8gB2-0001ek-67 for qemu-devel@nongnu.org; Wed, 06 Nov 2024 08:34:28 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t8gB0-0001a1-Ik for qemu-devel@nongnu.org; Wed, 06 Nov 2024 08:34:27 -0500 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-71e49ad46b1so5788654b3a.1 for ; Wed, 06 Nov 2024 05:34:26 -0800 (PST) Received: from grind.. ([189.79.22.174]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-720bc2eb64esm11749765b3a.168.2024.11.06.05.34.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 05:34:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1730900065; x=1731504865; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DV1MjcpJEaxpGdQy9Gd1H5P1SEK291KM48+bJCTEyMY=; b=EFtgFazXrLZ4iu4+A3e44Dh3zvYFIqGIuP/S7lYhOg7h2fgpgyvbqWNIljgJSmJ0ix woW62nrY+qBME1BXU0AlP5JuNpmXyTLsxN4LoCepAn9ZMckPSHSzwvZKs3WdjAHEOj0Y /rj0O6p8DjoKG1NOWllAU2tlpjsEWwwjsIC6uTkeUXJ/htzNSPiETEJuPGm0b1h2z6+J Xv7I2Vfocx4eOcPsG6TQKn3u+Y3QHHVk8mZBY8muantDp4hLMRD5x+JIVu2FnDkgP0D0 nmCm0Zt7HRbmydy4T3Ms3ar+vujYYPrb2ASUxIjU5esgvg8D/YYcLXdPtbzfaeZ9CpNF +XIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730900065; x=1731504865; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DV1MjcpJEaxpGdQy9Gd1H5P1SEK291KM48+bJCTEyMY=; b=a3V64H9ql4VqGNbmhd07NkTHVF20WNVS/7Cb2u3J7K9NWPJaWhoLeslmjU0izb0jDy 0ywNBWk3Iqyi0bM0j3zzXwWUXGfUo4Ne7AEGS4TcsFISOvSnMD6FFX3AHFxnO0MOVbw+ B+ldxvTOQankhP+UTdV6B3NKZbtrrxp+3XIongtxNu4e/Y0JxofbtWOs9JK03b0gk3BA kisEEXe238dgbQDeNpMcLTk+hm9di4w8T/93RGokK8kqGZch1SErVDv1nll6AT++qjzw ZEHArM5qO68qF9Lwbf7IsVsfUD4JpSih7R6ayEIPZemknvPQNK/TnVJjvBsLMi4OBH5C ixOg== X-Gm-Message-State: AOJu0YwPO2ckDwg+Bsni4CLg60uezZDwzgsmhQDG+SZUE9NXwl0aayKN 1yugDc4wdZu4ccO5k9RI6WOuMyDZh8a5EY+L1sFxL7BEEe5SZaWVYD7BjcldPftQjZIjgBlyqGT 4 X-Google-Smtp-Source: AGHT+IEB5oPOCmOejpH0nzi6fbQmE+UJZk87xvkXYpc4FLcMxHgPvZkwzaWVBIEQ6kjuFLWToEDaTw== X-Received: by 2002:a05:6a00:23ca:b0:71e:6122:5919 with SMTP id d2e1a72fcca58-7206306ed56mr52310286b3a.20.1730900064624; Wed, 06 Nov 2024 05:34:24 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-10.0 1/7] hw/riscv/riscv-iommu.c: add riscv_iommu_instance_init() Date: Wed, 6 Nov 2024 10:34:01 -0300 Message-ID: <20241106133407.604587-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241106133407.604587-1-dbarboza@ventanamicro.com> References: <20241106133407.604587-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1730900221093116600 Content-Type: text/plain; charset="utf-8" Move all the static initializion of the device to an init() function, leaving only the dynamic initialization to be done during realize. With this change s->cap is initialized with RISCV_IOMMU_CAP_DBG during init(), and realize() will increment s->cap with the extra caps. This will allow callers to add IOMMU capabilities before the realization. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/riscv-iommu.c | 71 +++++++++++++++++++++++------------------- 1 file changed, 39 insertions(+), 32 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index feb650549a..1893584028 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -2096,11 +2096,48 @@ static const MemoryRegionOps riscv_iommu_trap_ops = =3D { } }; =20 +static void riscv_iommu_instance_init(Object *obj) +{ + RISCVIOMMUState *s =3D RISCV_IOMMU(obj); + + /* Enable translation debug interface */ + s->cap =3D RISCV_IOMMU_CAP_DBG; + + /* Report QEMU target physical address space limits */ + s->cap =3D set_field(s->cap, RISCV_IOMMU_CAP_PAS, + TARGET_PHYS_ADDR_SPACE_BITS); + + /* TODO: method to report supported PID bits */ + s->pid_bits =3D 8; /* restricted to size of MemTxAttrs.pid */ + s->cap |=3D RISCV_IOMMU_CAP_PD8; + + /* register storage */ + s->regs_rw =3D g_new0(uint8_t, RISCV_IOMMU_REG_SIZE); + s->regs_ro =3D g_new0(uint8_t, RISCV_IOMMU_REG_SIZE); + s->regs_wc =3D g_new0(uint8_t, RISCV_IOMMU_REG_SIZE); + + /* Mark all registers read-only */ + memset(s->regs_ro, 0xff, RISCV_IOMMU_REG_SIZE); + + /* Device translation context cache */ + s->ctx_cache =3D g_hash_table_new_full(riscv_iommu_ctx_hash, + riscv_iommu_ctx_equal, + g_free, NULL); + + s->iot_cache =3D g_hash_table_new_full(riscv_iommu_iot_hash, + riscv_iommu_iot_equal, + g_free, NULL); + + s->iommus.le_next =3D NULL; + s->iommus.le_prev =3D NULL; + QLIST_INIT(&s->spaces); +} + static void riscv_iommu_realize(DeviceState *dev, Error **errp) { RISCVIOMMUState *s =3D RISCV_IOMMU(dev); =20 - s->cap =3D s->version & RISCV_IOMMU_CAP_VERSION; + s->cap |=3D s->version & RISCV_IOMMU_CAP_VERSION; if (s->enable_msi) { s->cap |=3D RISCV_IOMMU_CAP_MSI_FLAT | RISCV_IOMMU_CAP_MSI_MRIF; } @@ -2115,29 +2152,11 @@ static void riscv_iommu_realize(DeviceState *dev, E= rror **errp) s->cap |=3D RISCV_IOMMU_CAP_SV32X4 | RISCV_IOMMU_CAP_SV39X4 | RISCV_IOMMU_CAP_SV48X4 | RISCV_IOMMU_CAP_SV57X4; } - /* Enable translation debug interface */ - s->cap |=3D RISCV_IOMMU_CAP_DBG; - - /* Report QEMU target physical address space limits */ - s->cap =3D set_field(s->cap, RISCV_IOMMU_CAP_PAS, - TARGET_PHYS_ADDR_SPACE_BITS); - - /* TODO: method to report supported PID bits */ - s->pid_bits =3D 8; /* restricted to size of MemTxAttrs.pid */ - s->cap |=3D RISCV_IOMMU_CAP_PD8; =20 /* Out-of-reset translation mode: OFF (DMA disabled) BARE (passthrough= ) */ s->ddtp =3D set_field(0, RISCV_IOMMU_DDTP_MODE, s->enable_off ? RISCV_IOMMU_DDTP_MODE_OFF : RISCV_IOMMU_DDTP_MODE_= BARE); =20 - /* register storage */ - s->regs_rw =3D g_new0(uint8_t, RISCV_IOMMU_REG_SIZE); - s->regs_ro =3D g_new0(uint8_t, RISCV_IOMMU_REG_SIZE); - s->regs_wc =3D g_new0(uint8_t, RISCV_IOMMU_REG_SIZE); - - /* Mark all registers read-only */ - memset(s->regs_ro, 0xff, RISCV_IOMMU_REG_SIZE); - /* * Register complete MMIO space, including MSI/PBA registers. * Note, PCIDevice implementation will add overlapping MR for MSI/PBA, @@ -2195,19 +2214,6 @@ static void riscv_iommu_realize(DeviceState *dev, Er= ror **errp) memory_region_init_io(&s->trap_mr, OBJECT(dev), &riscv_iommu_trap_ops,= s, "riscv-iommu-trap", ~0ULL); address_space_init(&s->trap_as, &s->trap_mr, "riscv-iommu-trap-as"); - - /* Device translation context cache */ - s->ctx_cache =3D g_hash_table_new_full(riscv_iommu_ctx_hash, - riscv_iommu_ctx_equal, - g_free, NULL); - - s->iot_cache =3D g_hash_table_new_full(riscv_iommu_iot_hash, - riscv_iommu_iot_equal, - g_free, NULL); - - s->iommus.le_next =3D NULL; - s->iommus.le_prev =3D NULL; - QLIST_INIT(&s->spaces); } =20 static void riscv_iommu_unrealize(DeviceState *dev) @@ -2249,6 +2255,7 @@ static const TypeInfo riscv_iommu_info =3D { .name =3D TYPE_RISCV_IOMMU, .parent =3D TYPE_DEVICE, .instance_size =3D sizeof(RISCVIOMMUState), + .instance_init =3D riscv_iommu_instance_init, .class_init =3D riscv_iommu_class_init, }; =20 --=20 2.45.2 From nobody Sat Nov 23 20:24:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1730900335; cv=none; d=zohomail.com; s=zohoarc; b=U4zlaE+/Phhq+hmYFeh2A2BLR0pYgKzMchZHaFADuPnYAqXe73tsA4gs7uObTTY7102+ivu5cic47R4oIeLmm8ru7P/4VAxgoHLcR+9jzRVG6z0MyEj/H9HnjARurafd63jl/YGuT2jl8VTD9ZrioWJ0uRGiknUnjayxfiRZUj0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730900335; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=pf2EjqyLwqwTOez3ga3+F5Pahm+OzloPlTLYuNjieFM=; b=Kd00tzSzTEC5jK3BmwL+TF6KkV9bnVeK2gB7P5twTkPZe+ga0kYR/PMQEkGhQp3FK2ZCH8phAmiP8TR9iJZtzCiOThScLsuHhOJsz78q2xBhZ4UzVXfDQBQ9Q9eNzBGMflI3JFZXUQc4AEEYH4kkc3SWljIqy71TDN4sep2ocUA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 173090033554592.11491304500032; Wed, 6 Nov 2024 05:38:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t8gB7-0001gl-IB; Wed, 06 Nov 2024 08:34:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t8gB5-0001gD-6J for qemu-devel@nongnu.org; Wed, 06 Nov 2024 08:34:31 -0500 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t8gB3-0001aV-Ki for qemu-devel@nongnu.org; Wed, 06 Nov 2024 08:34:30 -0500 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-71e5a62031aso5457187b3a.1 for ; Wed, 06 Nov 2024 05:34:29 -0800 (PST) Received: from grind.. ([189.79.22.174]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-720bc2eb64esm11749765b3a.168.2024.11.06.05.34.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 05:34:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1730900067; x=1731504867; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pf2EjqyLwqwTOez3ga3+F5Pahm+OzloPlTLYuNjieFM=; b=ZzxWhADqt7ZVVuHWP7my0eBftigVZoPjKpq0XWRYPchYxpD3j2774Fj7JoX9ws+Abe QEazPbp6qu1veiRF0YImYjXVGGsRlWQ1EnenWQuJSl7qFZoouEvSgVbcOfo0/83JwtS+ HOZ/zeCLc7myR6FHsbeHUv7XmwGFcI/2ei8OjF0WkLJK4SbntXzMlp4Q7vij0YwX73th IX3BpbhPfIGCSNLuyJpfNKpGe0seossnuk04LoDSXQq5MN0jJPwGZ0xHGw/vsDePzs3s VkC/nAZm/sfhBuTU0gUKsECSMl/1A/o7YlKuBTvHfhNzimC3xlQiEvoZJ70/2ZRboGC8 IaEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730900067; x=1731504867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pf2EjqyLwqwTOez3ga3+F5Pahm+OzloPlTLYuNjieFM=; b=bGsUFrqgA+F+TAD4Sk8fFPrhnya7IJDmPvziFMLHf7fVDkViAhpVpgZKnm3P4qbOIW s8PMQ0LiYzrNgaRQWTzZO+UWU4ZvgHSOHt08gjNRhmYIApC4krga0TjZxMLCTwXuqqyf 86qxsHp4rFSeDlS9UVn896OgA+AJreybLGh2oNfSC77405vq8b/2Ztvs+T5gtFIjPt7l gq5t6SbRmYhXi3/+1TiVx0n9QtuyOBd4utmXyDS34pKh+5PCUUSXit1Nb2f0W8p61TZ/ 81boyoTTAWSdJyH8ul8cD12qgY+Ju8KGuAWupQAzvh0Eda45UGlKdQT/Hm6mm+Coy2nq DZag== X-Gm-Message-State: AOJu0YxpIFKf2fXtfahG0DBiPcJfRxIgm0glnVBayQFotezmdKfWGiFZ BpvVOQg7gUZNyiY+nLwpHE7WJPKRewTkVtMkeBVUwS/YJB2enfo9OkPmS8KgDReiUvIgxIL0IC2 R X-Google-Smtp-Source: AGHT+IGvpBZeKDdfyohdAZ7akkklUaDWZfMd8PB+00HtZySuwPdgiYSsgPz9HPvZkS42TRtsUnptOw== X-Received: by 2002:a05:6a00:1708:b0:71d:f423:e6cc with SMTP id d2e1a72fcca58-720c98d5c3dmr28187651b3a.8.1730900067539; Wed, 06 Nov 2024 05:34:27 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-10.0 2/7] hw/riscv/riscv-iommu: parametrize CAP.IGS Date: Wed, 6 Nov 2024 10:34:02 -0300 Message-ID: <20241106133407.604587-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241106133407.604587-1-dbarboza@ventanamicro.com> References: <20241106133407.604587-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1730900337558116600 Content-Type: text/plain; charset="utf-8" Interrupt Generation Support (IGS) is a capability that is tied to the interrupt deliver mechanism, not with the core IOMMU emulation. We should allow device implementations to set IGS as they wish. A new helper is added to make it easier for device impls to set IGS. Use it in our existing IOMMU device (riscv-iommu-pci) to set RISCV_IOMMU_CAPS_IGS_MSI. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/riscv-iommu-bits.h | 6 ++++++ hw/riscv/riscv-iommu-pci.c | 1 + hw/riscv/riscv-iommu.c | 5 +++++ hw/riscv/riscv-iommu.h | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h index 6359ae0353..485f36b9c9 100644 --- a/hw/riscv/riscv-iommu-bits.h +++ b/hw/riscv/riscv-iommu-bits.h @@ -88,6 +88,12 @@ struct riscv_iommu_pq_record { #define RISCV_IOMMU_CAP_PD17 BIT_ULL(39) #define RISCV_IOMMU_CAP_PD20 BIT_ULL(40) =20 +enum riscv_iommu_igs_modes { + RISCV_IOMMU_CAP_IGS_MSI =3D 0, + RISCV_IOMMU_CAP_IGS_WSI, + RISCV_IOMMU_CAP_IGS_BOTH +}; + /* 5.4 Features control register (32bits) */ #define RISCV_IOMMU_REG_FCTL 0x0008 #define RISCV_IOMMU_FCTL_BE BIT(0) diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c index a42242532d..4ce9bf6b78 100644 --- a/hw/riscv/riscv-iommu-pci.c +++ b/hw/riscv/riscv-iommu-pci.c @@ -155,6 +155,7 @@ static void riscv_iommu_pci_init(Object *obj) qdev_alias_all_properties(DEVICE(iommu), obj); =20 iommu->icvec_avail_vectors =3D RISCV_IOMMU_PCI_ICVEC_VECTORS; + riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_MSI); } =20 static Property riscv_iommu_pci_properties[] =3D { diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 1893584028..d95b4b95d8 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -2096,6 +2096,11 @@ static const MemoryRegionOps riscv_iommu_trap_ops = =3D { } }; =20 +void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode) +{ + s->cap =3D set_field(s->cap, RISCV_IOMMU_CAP_IGS, mode); +} + static void riscv_iommu_instance_init(Object *obj) { RISCVIOMMUState *s =3D RISCV_IOMMU(obj); diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h index da3f03440c..f9f2827808 100644 --- a/hw/riscv/riscv-iommu.h +++ b/hw/riscv/riscv-iommu.h @@ -21,6 +21,9 @@ =20 #include "qom/object.h" #include "hw/riscv/iommu.h" +#include "hw/riscv/riscv-iommu-bits.h" + +typedef enum riscv_iommu_igs_modes riscv_iommu_igs_mode; =20 struct RISCVIOMMUState { /*< private >*/ @@ -85,6 +88,7 @@ struct RISCVIOMMUState { =20 void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus, Error **errp); +void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode= ); =20 /* private helpers */ =20 --=20 2.45.2 From nobody Sat Nov 23 20:24:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1730900131; cv=none; d=zohomail.com; s=zohoarc; b=FBsK4yE59O8KIcbVlYQLWghUUPcVwjhxcLlVX1L70qr+LCMNPQs4MarY10eYyJPbGrkHWGqTrg1TFB1GmGYmmnFlZuLRfIxESZGAmOzjxy4IyKZvtXYSCSafdSntN7E/t1Ah+SdKgbB6aw4CXq8g9vlKN30ulqWqkwu8os/h7Ig= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730900131; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CfJEur4IrmO6iNqhGkNHqo96+uRQo7JpR47tGh3SBH0=; b=X4XNm/61X+CQEny7IpAmS5VYBDodzQ5Jv/2Z5bQWKy7/lESE/KScctWkZK7kAKx1b/dE8s8xy0Uw9cGLlt35G4RvL54PlwHF5NdAbNIdsjemm1i6XOGlgO0zxfYlCoHnIXGUqxNfQyIhL9Ap+6UeJCMCxEsW2CkcKvLTZpZsyQE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1730900131195253.0297613744841; Wed, 6 Nov 2024 05:35:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t8gBB-0001hU-9y; Wed, 06 Nov 2024 08:34:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t8gB8-0001gv-8c for qemu-devel@nongnu.org; Wed, 06 Nov 2024 08:34:34 -0500 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t8gB6-0001at-AC for qemu-devel@nongnu.org; Wed, 06 Nov 2024 08:34:34 -0500 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-720cb6ac25aso5202490b3a.3 for ; Wed, 06 Nov 2024 05:34:31 -0800 (PST) Received: from grind.. ([189.79.22.174]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-720bc2eb64esm11749765b3a.168.2024.11.06.05.34.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 05:34:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1730900071; x=1731504871; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CfJEur4IrmO6iNqhGkNHqo96+uRQo7JpR47tGh3SBH0=; b=iFsubFUekQGD6EpsMiLzcFK4mRl6a7uX1bDQ9iWkpaadl6Ors7fWku8aGK34rPww9m E+ULH+yBwlINwszf9otI5t4p05RPa5+d7cvibk+X5De5DX6QcPjJK8xtlyE11PowmPNu eXRu2n+TgozIJmReOr9bnP80svM3pezRU3iMopHPVXqsFeaMwkQPzCVwLiFevfSNU4I+ 1vzFwWNvVBMIbZKZfY2m7O8Ze+k8yfaCGljro1+LvLyyMu9Qfem5CglOX9pSQwXr2xiS p3pt3hv1pAeiNABuB8tUkMIIy9DmH7mmAoxhBY10xH7o7SvP++GpZwOfmcX6KbWbNNvJ t8og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730900071; x=1731504871; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CfJEur4IrmO6iNqhGkNHqo96+uRQo7JpR47tGh3SBH0=; b=TDvBjPWilp3BeH01IPaX+trff2kJ8AZlqJle2/RUdFcLHLCKr8/xc3BUcLKKVtQANX Y/H1YczOsg78SQQk6LPABf69RbRasEA8SkqDwOcIB/lQojsjpQNRo4VfDYyxp8NH2s/C YGzTVRmcagXhaay+QC/eUWUJ5/5znWkjsOkk33LhmflVKCbnr40yDg07AidyFqna9p9X 6QhRktrxbfi1f1PhKvzTvE+uqytEHV9MjrQ7ZR6ZTmSOhkYNC0LDcE86SVmSa4m15czp ipn6W5rhO+DDf65eZbTxxKiwi7wrc+2T58YmFUU9K6TgsnnKGe9dU/rkbSOLVXdp4BUK xcGQ== X-Gm-Message-State: AOJu0YxDUwWSKCySZXQ3eyl/dRqy9FZpetkrwLP8KNAKdgHcm4v+rH7j LAR1l2tEruhzdEjEuuJ6EzU8EghwqO3IL3wisC6ah846riuKv8hNFv4trD0ZqQ3ySGBH00U1Zmo y X-Google-Smtp-Source: AGHT+IHND+dAC7/aHSiz7LYskE26ugOVYkxF/L0Xkke6WypdSpSYa0PHb3xGFh29AOUKyklM6lfHfA== X-Received: by 2002:a05:6a00:3cc8:b0:71e:b4ee:960d with SMTP id d2e1a72fcca58-72062fa1349mr55835619b3a.10.1730900070620; Wed, 06 Nov 2024 05:34:30 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Tomasz Jeznach , Daniel Henrique Barboza Subject: [PATCH for-10.0 3/7] hw/riscv: add riscv-iommu-sys platform device Date: Wed, 6 Nov 2024 10:34:03 -0300 Message-ID: <20241106133407.604587-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241106133407.604587-1-dbarboza@ventanamicro.com> References: <20241106133407.604587-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1730900135549116600 Content-Type: text/plain; charset="utf-8" From: Tomasz Jeznach This device models the RISC-V IOMMU as a sysbus device. The same design decisions taken in the riscv-iommu-pci device were kept, namely the existence of 4 vectors are available for each interrupt cause. The WSIs are emitted using the input of the s->notify() callback as a index to an IRQ list. The IRQ list starts at 'base_irq' and goes until base_irq + 3. This means that boards must have 4 contiguous IRQ lines available, starting from 'base_irq'. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/meson.build | 2 +- hw/riscv/riscv-iommu-sys.c | 128 +++++++++++++++++++++++++++++++++++++ hw/riscv/riscv-iommu.c | 3 +- include/hw/riscv/iommu.h | 4 ++ 4 files changed, 134 insertions(+), 3 deletions(-) create mode 100644 hw/riscv/riscv-iommu-sys.c diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index adbef8a9b2..3be13d7774 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -10,6 +10,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sif= ive_u.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfs= oc.c')) riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) -riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', '= riscv-iommu-pci.c')) +riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', '= riscv-iommu-pci.c', 'riscv-iommu-sys.c')) =20 hw_arch +=3D {'riscv': riscv_ss} diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c new file mode 100644 index 0000000000..4b82046ce9 --- /dev/null +++ b/hw/riscv/riscv-iommu-sys.c @@ -0,0 +1,128 @@ +/* + * QEMU emulation of an RISC-V IOMMU Platform Device + * + * Copyright (C) 2022-2023 Rivos Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "hw/irq.h" +#include "hw/pci/pci_bus.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/host-utils.h" +#include "qemu/module.h" +#include "qom/object.h" + +#include "riscv-iommu.h" + +#define RISCV_IOMMU_SYSDEV_ICVEC_VECTORS 0x3333 + +/* RISC-V IOMMU System Platform Device Emulation */ + +struct RISCVIOMMUStateSys { + SysBusDevice parent; + uint64_t addr; + uint32_t base_irq; + DeviceState *irqchip; + RISCVIOMMUState iommu; + qemu_irq irqs[RISCV_IOMMU_INTR_COUNT]; +}; + +static void riscv_iommu_sysdev_notify(RISCVIOMMUState *iommu, + unsigned vector) +{ + RISCVIOMMUStateSys *s =3D container_of(iommu, RISCVIOMMUStateSys, iomm= u); + uint32_t fctl =3D riscv_iommu_reg_get32(iommu, RISCV_IOMMU_REG_FCTL); + + /* We do not support MSIs yet */ + if (!(fctl & RISCV_IOMMU_FCTL_WSI)) { + return; + } + + qemu_irq_pulse(s->irqs[vector]); +} + +static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp) +{ + RISCVIOMMUStateSys *s =3D RISCV_IOMMU_SYS(dev); + SysBusDevice *sysdev =3D SYS_BUS_DEVICE(s); + PCIBus *pci_bus; + qemu_irq irq; + + qdev_realize(DEVICE(&s->iommu), NULL, errp); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iommu.regs_mr); + if (s->addr) { + sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, s->addr); + } + + pci_bus =3D (PCIBus *) object_resolve_path_type("", TYPE_PCI_BUS, NULL= ); + if (pci_bus) { + riscv_iommu_pci_setup_iommu(&s->iommu, pci_bus, errp); + } + + s->iommu.notify =3D riscv_iommu_sysdev_notify; + + /* 4 IRQs are defined starting from s->base_irq */ + for (int i =3D 0; i < RISCV_IOMMU_INTR_COUNT; i++) { + sysbus_init_irq(sysdev, &s->irqs[i]); + irq =3D qdev_get_gpio_in(s->irqchip, s->base_irq + i); + sysbus_connect_irq(sysdev, i, irq); + } +} + +static void riscv_iommu_sys_init(Object *obj) +{ + RISCVIOMMUStateSys *s =3D RISCV_IOMMU_SYS(obj); + RISCVIOMMUState *iommu =3D &s->iommu; + + object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU); + qdev_alias_all_properties(DEVICE(iommu), obj); + + iommu->icvec_avail_vectors =3D RISCV_IOMMU_SYSDEV_ICVEC_VECTORS; + riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_WSI); +} + +static Property riscv_iommu_sys_properties[] =3D { + DEFINE_PROP_UINT64("addr", RISCVIOMMUStateSys, addr, 0), + DEFINE_PROP_UINT32("base-irq", RISCVIOMMUStateSys, base_irq, 0), + DEFINE_PROP_LINK("irqchip", RISCVIOMMUStateSys, irqchip, + TYPE_DEVICE, DeviceState *), + DEFINE_PROP_END_OF_LIST(), +}; + +static void riscv_iommu_sys_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->realize =3D riscv_iommu_sys_realize; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + device_class_set_props(dc, riscv_iommu_sys_properties); +} + +static const TypeInfo riscv_iommu_sys =3D { + .name =3D TYPE_RISCV_IOMMU_SYS, + .parent =3D TYPE_SYS_BUS_DEVICE, + .class_init =3D riscv_iommu_sys_class_init, + .instance_init =3D riscv_iommu_sys_init, + .instance_size =3D sizeof(RISCVIOMMUStateSys), +}; + +static void riscv_iommu_register_sys(void) +{ + type_register_static(&riscv_iommu_sys); +} + +type_init(riscv_iommu_register_sys) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index d95b4b95d8..239f83f5bd 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -94,10 +94,9 @@ static uint8_t riscv_iommu_get_icvec_vector(uint32_t icv= ec, uint32_t vec_type) =20 static void riscv_iommu_notify(RISCVIOMMUState *s, int vec_type) { - const uint32_t fctl =3D riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_FCTL); uint32_t ipsr, icvec, vector; =20 - if (fctl & RISCV_IOMMU_FCTL_WSI || !s->notify) { + if (!s->notify) { return; } =20 diff --git a/include/hw/riscv/iommu.h b/include/hw/riscv/iommu.h index 80769a1400..fc20808553 100644 --- a/include/hw/riscv/iommu.h +++ b/include/hw/riscv/iommu.h @@ -33,4 +33,8 @@ typedef struct RISCVIOMMUSpace RISCVIOMMUSpace; OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStatePci, RISCV_IOMMU_PCI) typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci; =20 +#define TYPE_RISCV_IOMMU_SYS "riscv-iommu-device" +OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStateSys, RISCV_IOMMU_SYS) +typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys; 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([189.79.22.174]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-720bc2eb64esm11749765b3a.168.2024.11.06.05.34.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 05:34:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1730900074; x=1731504874; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=O4/wy95NAPbNDGrHX3ZK/QUzg1AOwh+OKLUN2DHjLmA=; b=RZ2ilJWBP5TUD5tNEysvsQ3zoAJV4Zq9GtjkU8oESZcaJCrsI0Kjt3V37kTEfa7NkI RbWpWHTFduc2ysTZ4KgVZwJVP+jtjOi3HlZmhDYRX21wrVuI2rKkfTjkuUO/a5ZlJhI0 wexYgGTfpTFKWmdGfeYy81qfaidtqg2LQV2FMoXdng0nua3vXWBw98BAxfWH+1FWEsM7 iwWDPwd3OSL6epnVObgV9CDJ1ljsss88BYoTUOuxzCrukrvKCHHZFlcvOZMbMXHHFUdE genYv5KdKU9WEqunkVt8RgWRjxDkmGQHXC8e1EmO+/EspgqjAhW4vzESZqUgGf1krYbK Exdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730900074; x=1731504874; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O4/wy95NAPbNDGrHX3ZK/QUzg1AOwh+OKLUN2DHjLmA=; b=lConzv8+YMfag4S/vgVL7FyyYFN5ehU/nuQg1AhVrNkhMq5ce//qG3CTZGtpuCtwrR QC9XDXLKqbK8i4/4tVOrjpxRgdmszUZZLjxsxmPe04IhpDaFbvWnTHwLpKGmpYARo/xV XE9dUJjhnjBjlDAQZ69XNXwo49RAr6Cdu2Aceg3QdyuFzhr+XObt7BZzuZEBW+UOqNmt B6h6p+NwtPW8tZ9GsgGUtCSWTT2R0Tf5tq3xab/shxOBTPPGh4QAcbr4gIW/xzUgQSPq Oc77GF2TvmySZqYfOZFiZ7gt8rz4fV2MEcIXU8PTLEm7IW0NSM0R8Olo2vwplXvDqFYG Ko3A== X-Gm-Message-State: AOJu0YxDndYydyoaAqqs9X70HiwTdT1c9sgc6Rk1/sI/xlL+Kp8eDh+8 n6o9H3saOq8rgfJh3NdSuzJI5lv2OHBaQobIhYYrzsKG8JJVU78UYcQp/UXmiM2cR43ZA3bpDqq W X-Google-Smtp-Source: AGHT+IHTBFxT1q6eOAfqrUjJtnR4zGcYG64EPajhjcv03w4H2cjRZUPL2jDe3uLLVv6CKuIfKjac7g== X-Received: by 2002:a05:6a00:1490:b0:71d:eb7d:20ed with SMTP id d2e1a72fcca58-720c98adb50mr28741690b3a.12.1730900073783; Wed, 06 Nov 2024 05:34:33 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Sunil V L , Daniel Henrique Barboza Subject: [PATCH for-10.0 4/7] hw/riscv/virt: Add IOMMU as platform device if the option is set Date: Wed, 6 Nov 2024 10:34:04 -0300 Message-ID: <20241106133407.604587-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241106133407.604587-1-dbarboza@ventanamicro.com> References: <20241106133407.604587-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1730900209126116600 Content-Type: text/plain; charset="utf-8" From: Sunil V L Add a new machine option called 'iommu-sys' that enables a riscv-iommu-sys platform device for the 'virt' machine. The option is default 'off'. The device will use IRQs 36 to 39. We will not support both riscv-iommu-sys and riscv-iommu-pci devices in the same board in this first implementation. If a riscv-iommu-pci device is added in the command line we will disable the riscv-iommu-sys device. Signed-off-by: Sunil V L Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/virt.c | 104 ++++++++++++++++++++++++++++++++++++++- include/hw/riscv/iommu.h | 2 + include/hw/riscv/virt.h | 6 ++- 3 files changed, 109 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 45a8c4f819..23d1380b86 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -33,6 +33,7 @@ #include "target/riscv/pmu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/iommu.h" +#include "hw/riscv/riscv-iommu-bits.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" @@ -76,6 +77,7 @@ static const MemMapEntry virt_memmap[] =3D { [VIRT_CLINT] =3D { 0x2000000, 0x10000 }, [VIRT_ACLINT_SSWI] =3D { 0x2F00000, 0x4000 }, [VIRT_PCIE_PIO] =3D { 0x3000000, 0x10000 }, + [VIRT_IOMMU_SYS] =3D { 0x3010000, 0x1000 }, [VIRT_PLATFORM_BUS] =3D { 0x4000000, 0x2000000 }, [VIRT_PLIC] =3D { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2= ) }, [VIRT_APLIC_M] =3D { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, @@ -853,7 +855,8 @@ static void create_fdt_virtio(RISCVVirtState *s, const = MemMapEntry *memmap, =20 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, uint32_t irq_pcie_phandle, - uint32_t msi_pcie_phandle) + uint32_t msi_pcie_phandle, + uint32_t iommu_sys_phandle) { g_autofree char *name =3D NULL; MachineState *ms =3D MACHINE(s); @@ -887,6 +890,12 @@ static void create_fdt_pcie(RISCVVirtState *s, const M= emMapEntry *memmap, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); =20 + if (virt_is_iommu_sys_enabled(s)) { + qemu_fdt_setprop_cells(ms->fdt, name, "iommu-map", + 0, iommu_sys_phandle, 0, 0, 0, + iommu_sys_phandle, 0, 0xffff); + } + create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); } =20 @@ -1033,6 +1042,44 @@ static void create_fdt_virtio_iommu(RISCVVirtState *= s, uint16_t bdf) bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); } =20 +static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip, + uint32_t *iommu_sys_phandle) +{ + const char comp[] =3D "riscv,iommu"; + void *fdt =3D MACHINE(s)->fdt; + uint32_t iommu_phandle; + g_autofree char *iommu_node =3D NULL; + hwaddr addr =3D s->memmap[VIRT_IOMMU_SYS].base; + hwaddr size =3D s->memmap[VIRT_IOMMU_SYS].size; + uint32_t iommu_irq_map[RISCV_IOMMU_INTR_COUNT] =3D { + IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_CQ, + IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_FQ, + IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PM, + IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PQ, + }; + + iommu_node =3D g_strdup_printf("/soc/iommu@%x", + (unsigned int) s->memmap[VIRT_IOMMU_SYS].ba= se); + iommu_phandle =3D qemu_fdt_alloc_phandle(fdt); + qemu_fdt_add_subnode(fdt, iommu_node); + + qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); + qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); + qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); + + qemu_fdt_setprop_cells(fdt, iommu_node, "reg", + addr >> 32, addr, size >> 32, size); + qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip); + + qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts", + iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW, + iommu_irq_map[1], FDT_IRQ_TYPE_EDGE_LOW, + iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW, + iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW); + + *iommu_sys_phandle =3D iommu_phandle; +} + static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf) { const char comp[] =3D "riscv,pci-iommu"; @@ -1061,6 +1108,7 @@ static void finalize_fdt(RISCVVirtState *s) { uint32_t phandle =3D 1, irq_mmio_phandle =3D 1, msi_pcie_phandle =3D 1; uint32_t irq_pcie_phandle =3D 1, irq_virtio_phandle =3D 1; + uint32_t iommu_sys_phandle =3D 1; =20 create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, @@ -1068,7 +1116,11 @@ static void finalize_fdt(RISCVVirtState *s) =20 create_fdt_virtio(s, virt_memmap, irq_virtio_phandle); =20 - create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle); + if (virt_is_iommu_sys_enabled(s)) { + create_fdt_iommu_sys(s, irq_mmio_phandle, &iommu_sys_phandle); + } + create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle, + iommu_sys_phandle); =20 create_fdt_reset(s, virt_memmap, &phandle); =20 @@ -1650,6 +1702,22 @@ static void virt_machine_init(MachineState *machine) create_fdt(s, memmap); } =20 + if (virt_is_iommu_sys_enabled(s)) { + DeviceState *iommu_sys =3D qdev_new(TYPE_RISCV_IOMMU_SYS); + + object_property_set_uint(OBJECT(iommu_sys), "addr", + s->memmap[VIRT_IOMMU_SYS].base, + &error_fatal); + object_property_set_uint(OBJECT(iommu_sys), "base-irq", + IOMMU_SYS_IRQ, + &error_fatal); + object_property_set_link(OBJECT(iommu_sys), "irqchip", + OBJECT(mmio_irqchip), + &error_fatal); + + sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal); + } + s->machine_done.notify =3D virt_machine_done; qemu_add_machine_init_done_notifier(&s->machine_done); } @@ -1663,6 +1731,7 @@ static void virt_machine_instance_init(Object *obj) s->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); s->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); s->acpi =3D ON_OFF_AUTO_AUTO; + s->iommu_sys =3D ON_OFF_AUTO_AUTO; } =20 static char *virt_get_aia_guests(Object *obj, Error **errp) @@ -1735,6 +1804,28 @@ static void virt_set_aclint(Object *obj, bool value,= Error **errp) s->have_aclint =3D value; } =20 +bool virt_is_iommu_sys_enabled(RISCVVirtState *s) +{ + return s->iommu_sys =3D=3D ON_OFF_AUTO_ON; +} + +static void virt_get_iommu_sys(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + OnOffAuto iommu_sys =3D s->iommu_sys; + + visit_type_OnOffAuto(v, name, &iommu_sys, errp); +} + +static void virt_set_iommu_sys(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + + visit_type_OnOffAuto(v, name, &s->iommu_sys, errp); +} + bool virt_is_acpi_enabled(RISCVVirtState *s) { return s->acpi !=3D ON_OFF_AUTO_OFF; @@ -1761,10 +1852,12 @@ static HotplugHandler *virt_machine_get_hotplug_han= dler(MachineState *machine, DeviceState *dev) { MachineClass *mc =3D MACHINE_GET_CLASS(machine); + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(machine); =20 if (device_is_dynamic_sysbus(mc, dev) || object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) { + s->iommu_sys =3D ON_OFF_AUTO_OFF; return HOTPLUG_HANDLER(machine); } =20 @@ -1791,6 +1884,7 @@ static void virt_machine_device_plug_cb(HotplugHandle= r *hotplug_dev, =20 if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) { create_fdt_iommu(s, pci_get_bdf(PCI_DEVICE(dev))); + s->iommu_sys =3D ON_OFF_AUTO_OFF; } } =20 @@ -1853,6 +1947,12 @@ static void virt_machine_class_init(ObjectClass *oc,= void *data) NULL, NULL); object_class_property_set_description(oc, "acpi", "Enable ACPI"); + + object_class_property_add(oc, "iommu-sys", "OnOffAuto", + virt_get_iommu_sys, virt_set_iommu_sys, + NULL, NULL); + object_class_property_set_description(oc, "iommu-sys", + "Enable IOMMU platform device"); } =20 static const TypeInfo virt_machine_typeinfo =3D { diff --git a/include/hw/riscv/iommu.h b/include/hw/riscv/iommu.h index fc20808553..8a8acfc3f0 100644 --- a/include/hw/riscv/iommu.h +++ b/include/hw/riscv/iommu.h @@ -37,4 +37,6 @@ typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci; OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStateSys, RISCV_IOMMU_SYS) typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys; =20 +#define FDT_IRQ_TYPE_EDGE_LOW 1 + #endif diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index c0dc41ff9a..48a14bea2e 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -62,6 +62,7 @@ struct RISCVVirtState { OnOffAuto acpi; const MemMapEntry *memmap; struct GPEXHost *gpex_host; + OnOffAuto iommu_sys; }; =20 enum { @@ -84,7 +85,8 @@ enum { VIRT_PCIE_MMIO, VIRT_PCIE_PIO, VIRT_PLATFORM_BUS, - VIRT_PCIE_ECAM + VIRT_PCIE_ECAM, + VIRT_IOMMU_SYS, }; =20 enum { @@ -93,6 +95,7 @@ enum { VIRTIO_IRQ =3D 1, /* 1 to 8 */ VIRTIO_COUNT =3D 8, PCIE_IRQ =3D 0x20, /* 32 to 35 */ + IOMMU_SYS_IRQ =3D 0x24, /* 36-39 */ VIRT_PLATFORM_BUS_IRQ =3D 64, /* 64 to 95 */ }; =20 @@ -129,6 +132,7 @@ enum { 1 + FDT_APLIC_INT_CELLS) =20 bool virt_is_acpi_enabled(RISCVVirtState *s); +bool virt_is_iommu_sys_enabled(RISCVVirtState *s); void virt_acpi_setup(RISCVVirtState *vms); uint32_t imsic_num_bits(uint32_t count); =20 --=20 2.45.2 From nobody Sat Nov 23 20:24:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1730900169; 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([189.79.22.174]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-720bc2eb64esm11749765b3a.168.2024.11.06.05.34.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 05:34:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1730900077; x=1731504877; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=//TDP2pofzp6yIYg3SZhcfCRS1G68mDibpjoR2NKauY=; b=WDMQpVRBeVOiXPW3mlz/thB30OKQsuqKF3tELeszM8fyFsW3q23tQTS2v5gFOYIEy/ goEm2j6Ja/bSJUpQtsPDtzWppJtfgZsmjhpPOX5KDB6WH14RjDZd5c6xD5mLqc9FIA3r PCiDAyo7SOPPgzxTUOKcYK/V1t3eqWf7L3GKuhl8jU4dsvVKA1c8kILf85ks0t9vojMl emgUqljJnidkXzw2/R/6oLSZ8p3I49D7lEFHEs5kFq4X0qbfsbhxaf+lKR6g03nq8E7K UYXdoy/kcLjPzea2DDzXsfGLz/lj07kpLUeKYHc06GUV42gx0c9mzjh7SIYFcUzM6l41 Iypg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730900077; x=1731504877; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=//TDP2pofzp6yIYg3SZhcfCRS1G68mDibpjoR2NKauY=; b=ZN79MFVxa9U81cFvUIZbcs/cHsA1X5Il6joCXBrSrIigU3AMvFYXCkELdeChKo29Mc hTBAwf6+jbyB1B7uummx5hpYOzlTAevj8XWPzXmY0FqkfCOx9lD0BOl8dbno8duSCguP FyvG3Y2my1WNFtGLtNqNiVNeflPRc0piOZ3+j1HE9Lyc0REFqanvxEbiXpXbyIkhFOhO wxlsfv7Imn4wgma2G984xMr/SMG5Urk9iKkrQwSLe7ChAzmKI2Rg4ypp8bx5HCRNeBWU lvF7FxmaVv05gD7FTum8nu0ZgLkkY/1is3HPWth/jxvtMeJtr8yuB8T56V3JGe3NIfCV 9guA== X-Gm-Message-State: AOJu0YzoaYJKqVRCYTA856E3XU0Qi5waVybpZ0CxTZOWNBnDI5Bv9E/y +ERpx7uMhL0t1ZRAqDckhT9C25XLeAtGor4JYXOQrz8Gch5+MIwS7cXcrwV/Wlz2ZBsxWt8aUct k X-Google-Smtp-Source: AGHT+IHk7F++mydK24yaUYc5lI+P683kwI12cCbAjL7g1HIkYpQDwi9Vny4tqNejtZElGXIzoSgYIg== X-Received: by 2002:a05:6a00:331b:b0:721:19bc:4bf4 with SMTP id d2e1a72fcca58-72119bc986cmr18065922b3a.23.1730900076659; Wed, 06 Nov 2024 05:34:36 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-10.0 5/7] hw/riscv/virt.c, riscv-iommu-sys.c: add MSIx support Date: Wed, 6 Nov 2024 10:34:05 -0300 Message-ID: <20241106133407.604587-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241106133407.604587-1-dbarboza@ventanamicro.com> References: <20241106133407.604587-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1730900171264116600 Content-Type: text/plain; charset="utf-8" MSIx support is added in the RISC-V IOMMU platform device by including the required MSIx facilities to alow software to properly setup the MSIx subsystem. We took inspiration of what is being done in the riscv-iommu-pci device, mainly msix_init() and msix_notify(), while keeping in mind that riscv-iommu-sys isn't a true PCI device and we don't need to copy/paste all the contents of these MSIx functions. Two extra MSI MemoryRegions were added: 'msix-table' and 'msix-pba'. They are used to manage r/w of the MSI table and Pending Bit Array (PBA) respectively. Both are subregions of the main IOMMU memory region, iommu->regs_mr, initialized during riscv_iommu_realize(), and each one has their own handlers for MSIx reads and writes. This is the expected memory map when using this device in the 'virt' machine: 0000000003010000-0000000003010fff (prio 0, i/o): riscv-iommu-regs 0000000003010300-000000000301034f (prio 0, i/o): msix-table 0000000003010400-0000000003010407 (prio 0, i/o): msix-pba We're now able to set IGS to RISCV_IOMMU_CAP_IGS_BOTH, and userspace is free to decide which interrupt model to use. Enabling MSIx support for this device in the 'virt' machine requires adding 'msi-parent' in the iommu-sys DT. Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- hw/riscv/riscv-iommu-sys.c | 116 +++++++++++++++++++++++++++++++++++-- hw/riscv/trace-events | 2 + hw/riscv/virt.c | 6 +- 3 files changed, 119 insertions(+), 5 deletions(-) diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c index 4b82046ce9..a0ef67a20b 100644 --- a/hw/riscv/riscv-iommu-sys.c +++ b/hw/riscv/riscv-iommu-sys.c @@ -26,11 +26,15 @@ #include "qemu/host-utils.h" #include "qemu/module.h" #include "qom/object.h" +#include "exec/exec-all.h" +#include "trace.h" =20 #include "riscv-iommu.h" =20 #define RISCV_IOMMU_SYSDEV_ICVEC_VECTORS 0x3333 =20 +#define RISCV_IOMMU_PCI_MSIX_VECTORS 5 + /* RISC-V IOMMU System Platform Device Emulation */ =20 struct RISCVIOMMUStateSys { @@ -39,21 +43,123 @@ struct RISCVIOMMUStateSys { uint32_t base_irq; DeviceState *irqchip; RISCVIOMMUState iommu; + + /* Wired int support */ qemu_irq irqs[RISCV_IOMMU_INTR_COUNT]; + + /* Memory Regions for MSIX table and pending bit entries. */ + MemoryRegion msix_table_mmio; + MemoryRegion msix_pba_mmio; + uint8_t *msix_table; + uint8_t *msix_pba; +}; + +static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr, + unsigned size) +{ + RISCVIOMMUStateSys *s =3D opaque; + + g_assert(addr + size <=3D RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTR= Y_SIZE); + return pci_get_long(s->msix_table + addr); +} + +static void msix_table_mmio_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + RISCVIOMMUStateSys *s =3D opaque; + + g_assert(addr + size <=3D RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTR= Y_SIZE); + pci_set_long(s->msix_table + addr, val); +} + +static const MemoryRegionOps msix_table_mmio_ops =3D { + .read =3D msix_table_mmio_read, + .write =3D msix_table_mmio_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 8, + }, + .impl =3D { + .max_access_size =3D 4, + }, +}; + +static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr, + unsigned size) +{ + RISCVIOMMUStateSys *s =3D opaque; + + return pci_get_long(s->msix_pba + addr); +} + +static void msix_pba_mmio_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ +} + +static const MemoryRegionOps msix_pba_mmio_ops =3D { + .read =3D msix_pba_mmio_read, + .write =3D msix_pba_mmio_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 8, + }, + .impl =3D { + .max_access_size =3D 4, + }, }; =20 +static void riscv_iommu_sysdev_init_msi(RISCVIOMMUStateSys *s, + uint32_t n_vectors) +{ + RISCVIOMMUState *iommu =3D &s->iommu; + uint32_t table_size =3D table_size =3D n_vectors * PCI_MSIX_ENTRY_SIZE; + uint32_t table_offset =3D RISCV_IOMMU_REG_MSI_CONFIG; + uint32_t pba_size =3D QEMU_ALIGN_UP(n_vectors, 64) / 8; + uint32_t pba_offset =3D RISCV_IOMMU_REG_MSI_CONFIG + 256; + + s->msix_table =3D g_malloc0(table_size); + s->msix_pba =3D g_malloc0(pba_size); + + memory_region_init_io(&s->msix_table_mmio, OBJECT(s), &msix_table_mmio= _ops, + s, "msix-table", table_size); + memory_region_add_subregion(&iommu->regs_mr, table_offset, + &s->msix_table_mmio); + + memory_region_init_io(&s->msix_pba_mmio, OBJECT(s), &msix_pba_mmio_ops= , s, + "msix-pba", pba_size); + memory_region_add_subregion(&iommu->regs_mr, pba_offset, + &s->msix_pba_mmio); +} + +static void riscv_iommu_sysdev_send_MSI(RISCVIOMMUStateSys *s, + uint32_t vector) +{ + uint8_t *table_entry =3D s->msix_table + vector * PCI_MSIX_ENTRY_SIZE; + uint64_t msi_addr =3D pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_= ADDR); + uint32_t msi_data =3D pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA); + MemTxResult result; + + address_space_stl_le(&address_space_memory, msi_addr, + msi_data, MEMTXATTRS_UNSPECIFIED, &result); + trace_riscv_iommu_sys_msi_sent(vector, msi_addr, msi_data, result); +} + static void riscv_iommu_sysdev_notify(RISCVIOMMUState *iommu, unsigned vector) { RISCVIOMMUStateSys *s =3D container_of(iommu, RISCVIOMMUStateSys, iomm= u); uint32_t fctl =3D riscv_iommu_reg_get32(iommu, RISCV_IOMMU_REG_FCTL); =20 - /* We do not support MSIs yet */ - if (!(fctl & RISCV_IOMMU_FCTL_WSI)) { + if (fctl & RISCV_IOMMU_FCTL_WSI) { + qemu_irq_pulse(s->irqs[vector]); + trace_riscv_iommu_sys_irq_sent(vector); return; } =20 - qemu_irq_pulse(s->irqs[vector]); + riscv_iommu_sysdev_send_MSI(s, vector); } =20 static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp) @@ -82,6 +188,8 @@ static void riscv_iommu_sys_realize(DeviceState *dev, Er= ror **errp) irq =3D qdev_get_gpio_in(s->irqchip, s->base_irq + i); sysbus_connect_irq(sysdev, i, irq); } + + riscv_iommu_sysdev_init_msi(s, RISCV_IOMMU_PCI_MSIX_VECTORS); } =20 static void riscv_iommu_sys_init(Object *obj) @@ -93,7 +201,7 @@ static void riscv_iommu_sys_init(Object *obj) qdev_alias_all_properties(DEVICE(iommu), obj); =20 iommu->icvec_avail_vectors =3D RISCV_IOMMU_SYSDEV_ICVEC_VECTORS; - riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_WSI); + riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_BOTH); } =20 static Property riscv_iommu_sys_properties[] =3D { diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events index 0527c56c91..94facbb8b1 100644 --- a/hw/riscv/trace-events +++ b/hw/riscv/trace-events @@ -15,3 +15,5 @@ riscv_iommu_icvec_write(uint32_t orig, uint32_t actual) "= ICVEC write: incoming 0 riscv_iommu_ats(const char *id, unsigned b, unsigned d, unsigned f, uint64= _t iova) "%s: translate request %04x:%02x.%u iova: 0x%"PRIx64 riscv_iommu_ats_inval(const char *id) "%s: dev-iotlb invalidate" riscv_iommu_ats_prgr(const char *id) "%s: dev-iotlb page request group res= ponse" +riscv_iommu_sys_irq_sent(uint32_t vector) "IRQ sent to vector %u" +riscv_iommu_sys_msi_sent(uint32_t vector, uint64_t msi_addr, uint32_t msi_= data, uint32_t result) "MSI sent to vector %u msi_addr 0x%lx msi_data 0x%x = result %u" diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 23d1380b86..281fc65cc6 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1043,6 +1043,7 @@ static void create_fdt_virtio_iommu(RISCVVirtState *s= , uint16_t bdf) } =20 static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip, + uint32_t msi_phandle, uint32_t *iommu_sys_phandle) { const char comp[] =3D "riscv,iommu"; @@ -1077,6 +1078,8 @@ static void create_fdt_iommu_sys(RISCVVirtState *s, u= int32_t irq_chip, iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW, iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW); =20 + qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle); + *iommu_sys_phandle =3D iommu_phandle; } =20 @@ -1117,7 +1120,8 @@ static void finalize_fdt(RISCVVirtState *s) create_fdt_virtio(s, virt_memmap, irq_virtio_phandle); =20 if (virt_is_iommu_sys_enabled(s)) { - create_fdt_iommu_sys(s, irq_mmio_phandle, &iommu_sys_phandle); + create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle, + &iommu_sys_phandle); } create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle, iommu_sys_phandle); --=20 2.45.2 From nobody Sat Nov 23 20:24:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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([189.79.22.174]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-720bc2eb64esm11749765b3a.168.2024.11.06.05.34.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 05:34:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1730900079; x=1731504879; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vWu4P2SNKyMxaSD2TWANA06+/Q0GELUCulyrPEKTgP0=; b=L+EcCCHzSowSR91ONqNe8CL4MPfo2yuonfKDkTQ8I2oE/6+QJHsO88cHe+0BKy5Rfb HTBevYSkFSeN8QaNd7rp2Ni05EdC7iJblP40c3vS6zoonghne36QFWeLEKAuWt0rL8/V 5T4UQ2jPleOiYHpUdsir/W8sBg2y7zjBbFhq2uYE96XJqEEvNIuwLZeQbHKneRhfC4vj kGqjLbVvQhr9SBXfhG8enIOnJwYemG4XDOd9ivztxDQ7EfQdOz55l8lYRaok/I4X7IAz h0zZrkB988NKCpL6aaNAF9oY4/Y164NCszFbu2IOX2kG0m893TQPzeIjBSkh2ZUTxApX MIRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730900079; x=1731504879; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vWu4P2SNKyMxaSD2TWANA06+/Q0GELUCulyrPEKTgP0=; b=kTSRr8PD/5zBrggaPMYRST828SouyKasiToN/pj6nvGFLWbba3d87/YbBhOUlp1EnV HFN94RM7sV4X/+T8obYgkAb3LplIvjIYcODjrZty1KYlJJeuJ78N1Sw3SRi5IJQKKGlB GaXizrqURe1b5djr760R4GlfkSHlVd+1YozSkkzHb4UADsUJU7jeKrNAzMQ7Sggqfsmk 4bAve3cf14Jcad9pv79qFGvnyKXt6z7tfmEub9yAidlZWecOuUswhSkmbkmYmBfi+xr6 DFLslATAyPTIcuP7RFPqdxDbhTuP5+sXzubGoHYr0TbVFbim1u2dzpFZY8F4vAKza8O9 3rfQ== X-Gm-Message-State: AOJu0YyXXhs119wsIyXFfCMe+LsGLKHbjZPBRtmlnFgGQ4RE0EruNdNB 4m4SgOqm2rU57rsUJWYl0AO4d46K7aNQlTjzgf+Yzlwyr1PdGLKpWNhJ+1NIkTDC5Jn0a0ZSonH f X-Google-Smtp-Source: AGHT+IHeTr8149TqVjveSBpqIrsxmVQAy/lQNfnA9SXVcoPeBQ4fzsD4R9IfLfrOKt9cPxbe0IOsjQ== X-Received: by 2002:a05:6a20:7290:b0:1db:ed44:ba68 with SMTP id adf61e73a8af0-1dbed44baecmr10027917637.17.1730900079507; Wed, 06 Nov 2024 05:34:39 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-10.0 6/7] hw/riscv/riscv-iommu: implement reset protocol Date: Wed, 6 Nov 2024 10:34:06 -0300 Message-ID: <20241106133407.604587-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241106133407.604587-1-dbarboza@ventanamicro.com> References: <20241106133407.604587-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1730900165060116600 Content-Type: text/plain; charset="utf-8" Add a riscv_iommu_reset() helper in the base emulation code that implements the expected reset behavior as defined by the riscv-iommu spec. Devices can then use this helper in their own reset callbacks. Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- hw/riscv/riscv-iommu-pci.c | 20 ++++++++++++++++++++ hw/riscv/riscv-iommu-sys.c | 20 ++++++++++++++++++++ hw/riscv/riscv-iommu.c | 35 +++++++++++++++++++++++++++++++++++ hw/riscv/riscv-iommu.h | 1 + hw/riscv/trace-events | 2 ++ include/hw/riscv/iommu.h | 6 ++++-- 6 files changed, 82 insertions(+), 2 deletions(-) diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c index 4ce9bf6b78..51226c4877 100644 --- a/hw/riscv/riscv-iommu-pci.c +++ b/hw/riscv/riscv-iommu-pci.c @@ -31,6 +31,7 @@ #include "cpu_bits.h" #include "riscv-iommu.h" #include "riscv-iommu-bits.h" +#include "trace.h" =20 /* RISC-V IOMMU PCI Device Emulation */ #define RISCV_PCI_CLASS_SYSTEM_IOMMU 0x0806 @@ -66,6 +67,12 @@ typedef struct RISCVIOMMUStatePci { RISCVIOMMUState iommu; /* common IOMMU state */ } RISCVIOMMUStatePci; =20 +struct RISCVIOMMUPciClass { + /*< public >*/ + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + /* interrupt delivery callback */ static void riscv_iommu_pci_notify(RISCVIOMMUState *iommu, unsigned vector) { @@ -167,10 +174,23 @@ static Property riscv_iommu_pci_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static void riscv_iommu_pci_reset_hold(Object *obj, ResetType type) +{ + RISCVIOMMUStatePci *pci =3D RISCV_IOMMU_PCI(obj); + RISCVIOMMUState *iommu =3D &pci->iommu; + + riscv_iommu_reset(iommu); + + trace_riscv_iommu_pci_reset_hold(type); +} + static void riscv_iommu_pci_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.hold =3D riscv_iommu_pci_reset_hold; =20 k->realize =3D riscv_iommu_pci_realize; k->exit =3D riscv_iommu_pci_exit; diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c index a0ef67a20b..605979a0ac 100644 --- a/hw/riscv/riscv-iommu-sys.c +++ b/hw/riscv/riscv-iommu-sys.c @@ -54,6 +54,12 @@ struct RISCVIOMMUStateSys { uint8_t *msix_pba; }; =20 +struct RISCVIOMMUSysClass { + /*< public >*/ + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr, unsigned size) { @@ -212,9 +218,23 @@ static Property riscv_iommu_sys_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static void riscv_iommu_sys_reset_hold(Object *obj, ResetType type) +{ + RISCVIOMMUStateSys *sys =3D RISCV_IOMMU_SYS(obj); + RISCVIOMMUState *iommu =3D &sys->iommu; + + riscv_iommu_reset(iommu); + + trace_riscv_iommu_sys_reset_hold(type); +} + static void riscv_iommu_sys_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.hold =3D riscv_iommu_sys_reset_hold; + dc->realize =3D riscv_iommu_sys_realize; set_bit(DEVICE_CATEGORY_MISC, dc->categories); device_class_set_props(dc, riscv_iommu_sys_properties); diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 239f83f5bd..cf2019d6aa 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -2228,6 +2228,41 @@ static void riscv_iommu_unrealize(DeviceState *dev) g_hash_table_unref(s->ctx_cache); } =20 +void riscv_iommu_reset(RISCVIOMMUState *s) +{ + uint32_t reg_clr; + int ddtp_mode; + + /* + * Clear DDTP while setting DDTP_mode back to user + * initial setting. + */ + ddtp_mode =3D s->enable_off ? + RISCV_IOMMU_DDTP_MODE_OFF : RISCV_IOMMU_DDTP_MODE_BARE; + s->ddtp =3D set_field(0, RISCV_IOMMU_DDTP_MODE, ddtp_mode); + riscv_iommu_reg_set64(s, RISCV_IOMMU_REG_DDTP, s->ddtp); + + reg_clr =3D RISCV_IOMMU_CQCSR_CQEN | RISCV_IOMMU_CQCSR_CIE | + RISCV_IOMMU_CQCSR_CQON | RISCV_IOMMU_CQCSR_BUSY; + riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_CQCSR, 0, reg_clr); + + reg_clr =3D RISCV_IOMMU_FQCSR_FQEN | RISCV_IOMMU_FQCSR_FIE | + RISCV_IOMMU_FQCSR_FQON | RISCV_IOMMU_FQCSR_BUSY; + riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_FQCSR, 0, reg_clr); + + reg_clr =3D RISCV_IOMMU_PQCSR_PQEN | RISCV_IOMMU_PQCSR_PIE | + RISCV_IOMMU_PQCSR_PQON | RISCV_IOMMU_PQCSR_BUSY; + riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_PQCSR, 0, reg_clr); + + riscv_iommu_reg_mod64(s, RISCV_IOMMU_REG_TR_REQ_CTL, 0, + RISCV_IOMMU_TR_REQ_CTL_GO_BUSY); + + riscv_iommu_reg_set32(s, RISCV_IOMMU_REG_IPSR, 0); + + g_hash_table_remove_all(s->ctx_cache); + g_hash_table_remove_all(s->iot_cache); +} + static Property riscv_iommu_properties[] =3D { DEFINE_PROP_UINT32("version", RISCVIOMMUState, version, RISCV_IOMMU_SPEC_DOT_VER), diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h index f9f2827808..9424989df4 100644 --- a/hw/riscv/riscv-iommu.h +++ b/hw/riscv/riscv-iommu.h @@ -89,6 +89,7 @@ struct RISCVIOMMUState { void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus, Error **errp); void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode= ); +void riscv_iommu_reset(RISCVIOMMUState *s); =20 /* private helpers */ =20 diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events index 94facbb8b1..aaa2c0eb94 100644 --- a/hw/riscv/trace-events +++ b/hw/riscv/trace-events @@ -17,3 +17,5 @@ riscv_iommu_ats_inval(const char *id) "%s: dev-iotlb inva= lidate" riscv_iommu_ats_prgr(const char *id) "%s: dev-iotlb page request group res= ponse" riscv_iommu_sys_irq_sent(uint32_t vector) "IRQ sent to vector %u" riscv_iommu_sys_msi_sent(uint32_t vector, uint64_t msi_addr, uint32_t msi_= data, uint32_t result) "MSI sent to vector %u msi_addr 0x%lx msi_data 0x%x = result %u" +riscv_iommu_sys_reset_hold(int reset_type) "reset type %d" +riscv_iommu_pci_reset_hold(int reset_type) "reset type %d" diff --git a/include/hw/riscv/iommu.h b/include/hw/riscv/iommu.h index 8a8acfc3f0..b03339d75c 100644 --- a/include/hw/riscv/iommu.h +++ b/include/hw/riscv/iommu.h @@ -30,12 +30,14 @@ typedef struct RISCVIOMMUState RISCVIOMMUState; typedef struct RISCVIOMMUSpace RISCVIOMMUSpace; =20 #define TYPE_RISCV_IOMMU_PCI "riscv-iommu-pci" -OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStatePci, RISCV_IOMMU_PCI) +OBJECT_DECLARE_TYPE(RISCVIOMMUStatePci, RISCVIOMMUPciClass, RISCV_IOMMU_PC= I) typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci; +typedef struct RISCVIOMMUPciClass RISCVIOMMUPciClass; =20 #define TYPE_RISCV_IOMMU_SYS "riscv-iommu-device" -OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStateSys, RISCV_IOMMU_SYS) +OBJECT_DECLARE_TYPE(RISCVIOMMUStateSys, RISCVIOMMUSysClass, RISCV_IOMMU_SY= S) typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys; +typedef struct RISCVIOMMUSysClass RISCVIOMMUSysClass; =20 #define FDT_IRQ_TYPE_EDGE_LOW 1 =20 --=20 2.45.2 From nobody Sat Nov 23 20:24:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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([189.79.22.174]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-720bc2eb64esm11749765b3a.168.2024.11.06.05.34.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 05:34:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1730900082; x=1731504882; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vd7uhK27iZe8oGBrkgQRn9OqHPo3B4lI9DZBvvRNQAw=; b=ED6dm29JhmItjFuKV6GGt3d82psMLkklaDgjBkidusGR0UAG76JEdfVHRm9IZss2TC xeDN6V57nmqtymDp2vm19ZZ+fwc+dK2bQx8jyGv+gefgFUSlMoGlcmSVKGC3E/ho3uTr cKCx6h6Hjqa9GUOx2B/Pbu5odwaVz6b0rWO1AjaEo5OfWpQ6YwjfCDraxNxKC9w9pjNr aXONisjd4QQX3AICNOvq+aYQarO+WEWBmW1PushUI1XvhmfejzeiMLBBHhWQI0+wJpSH dtBKLjvCYUP63LXSwneOjQBnNzVu7v2jybtBTKiMhHbsS8Kre0/eLLIU+YHy5qj3MZYA XiqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730900082; x=1731504882; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vd7uhK27iZe8oGBrkgQRn9OqHPo3B4lI9DZBvvRNQAw=; b=GS1cXzGrXi5dy9nBkqjveL/5/kARGknHaBE/ExkhfogI12p0hgOjkIXMYc7JTVGQVM pCSP4MLh7Gi9C8zxS/Wst49sCksjJtgrB0jzhM7JBfRMxdOeyIn1VhWamJC0y2dUfoS2 wCM2GOTC1y+TNlovJV5FLyz2YGFvv8CM7/3acUkFnyjOzdpYWVfmkwFl1GVxNZjbsn6y SfiZjFK4+KhNojvEUowz5uaVCdzKzes7dhou/lzh/WSiqBRliHDmigl6/ThYZn0semef 3ifrmp+B5K2s513QZDL9lOKgj8a2duAHkYkMcPeskR3kC0NMUdIo90d7L0T+QsAIekpE XMiw== X-Gm-Message-State: AOJu0YwbV9OrIpwOl9Th5Cz1eOZsw7oTIGqhp0JN1VYFS99sBrVccBWF in72R8y7bShkOqigrGXbqToPdc9VFjsmyDRYaLaKw4gy0VjxqrMJuR5Ru1z3V1hM4lEA0Yzn2an e X-Google-Smtp-Source: AGHT+IEZKfSgSVAVgJgnMiXagw99BIg7rWlohlX9ZyOP82KF7HOyFN5o02dadtm82Nn9O2VsmgZWoA== X-Received: by 2002:a05:6a00:1303:b0:71e:4df3:b1d3 with SMTP id d2e1a72fcca58-72062f80b4cmr58116023b3a.4.1730900082498; Wed, 06 Nov 2024 05:34:42 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-10.0 7/7] docs/specs: add riscv-iommu-sys information Date: Wed, 6 Nov 2024 10:34:07 -0300 Message-ID: <20241106133407.604587-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241106133407.604587-1-dbarboza@ventanamicro.com> References: <20241106133407.604587-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1730900167207116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- docs/specs/riscv-iommu.rst | 30 +++++++++++++++++++++++++++--- docs/system/riscv/virt.rst | 10 ++++++++++ 2 files changed, 37 insertions(+), 3 deletions(-) diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.rst index 463f4cffb6..b1538c9ead 100644 --- a/docs/specs/riscv-iommu.rst +++ b/docs/specs/riscv-iommu.rst @@ -6,9 +6,9 @@ RISC-V IOMMU support for RISC-V machines QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec version 1.0 `iommu1.0`_. =20 -The emulation includes a PCI reference device, riscv-iommu-pci, that QEMU -RISC-V boards can use. The 'virt' RISC-V machine is compatible with this -device. +The emulation includes a PCI reference device (riscv-iommu-pci) and a plat= form +bus device (riscv-iommu-sys) that QEMU RISC-V boards can use. The 'virt' +RISC-V machine is compatible with both devices. =20 riscv-iommu-pci reference device -------------------------------- @@ -83,6 +83,30 @@ Several options are available to control the capabilitie= s of the device, namely: - "s-stage": enable s-stage support - "g-stage": enable g-stage support =20 +riscv-iommu-sys device +---------------------- + +This device implements the RISC-V IOMMU emulation as a platform bus device= that +RISC-V boards can use. + +For the 'virt' board the device is disabled by default. To enable it use = the +'iommu-sys' machine option: + +.. code-block:: bash + + $ qemu-system-riscv64 -M virt,iommu-sys=3Don (...) + +There is no options to configure the capabilities of this device in the 'v= irt' +board using the QEMU command line. The device is configured with the foll= owing +riscv-iommu options: + +- "ioatc-limit": default value (2Mb) +- "intremap": enabled +- "ats": enabled +- "off": on (DMA disabled) +- "s-stage": enabled +- "g-stage": enabled + .. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/downlo= ad/v1.0/riscv-iommu.pdf =20 .. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tje= znach@rivosinc.com/ diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst index 8e9a2e4dda..537aac0340 100644 --- a/docs/system/riscv/virt.rst +++ b/docs/system/riscv/virt.rst @@ -94,6 +94,12 @@ command line: =20 $ qemu-system-riscv64 -M virt -device riscv-iommu-pci (...) =20 +It also has support for the riscv-iommu-sys platform device: + +.. code-block:: bash + + $ qemu-system-riscv64 -M virt,iommu-sys=3Don (...) + Refer to :ref:`riscv-iommu` for more information on how the RISC-V IOMMU s= upport works. =20 @@ -129,6 +135,10 @@ The following machine-specific options are supported: having AIA IMSIC (i.e. "aia=3Daplic-imsic" selected). When not specified, the default number of per-HART VS-level AIA IMSIC pages is 0. =20 +- iommu-sys=3D[on|off] + + Enables the riscv-iommu-sys platform device. Defaults to 'off'. + Running Linux kernel -------------------- =20 --=20 2.45.2