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[82.218.84.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5cee6a9a41bsm1467773a12.14.2024.11.05.08.00.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 08:00:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=philjordan-eu.20230601.gappssmtp.com; s=20230601; t=1730822455; x=1731427255; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pLGSZwK3UxPn1kZOhpJnWP1fni4o9+7TVcds9qkz8Vo=; b=tCJmQcFHwtlC/FhiB5h/Z2lkbIEDMixN11ycCF2H2QUq/UoiwrtjDKzwlY/kndnLw2 Qq2PF0u52EtDI/l4DKSIjhj3/JcUcMu8vq1aMMWpsy5Pdxn/7VqArbvOj+ZB2YsUDCbu +VAvmNR/nEbjL0W6L+fZAmzsF8Lw7GQBSiEStbvbD56uFqoNeXwAOz5k1CO6l3uH4qvj hiAIX2Gy8mkkbWm/BsB3FAAJr+Qi2/4YLa34qSWMdWQ34V+eMjuIIvxRfsLQIFy+5fhe ay4LD63e3DE9G3hcO96j76poLOUFyKteK11zKjtCjQ4Egxgjcmj1tpNgoCTsDiDOfCoQ Wg6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730822455; x=1731427255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pLGSZwK3UxPn1kZOhpJnWP1fni4o9+7TVcds9qkz8Vo=; b=YHqzDT33/6uocthJcNVnr+FsURJH/hp6Oo21mr8Z28/WIyhHOcpYdv63yEynzD0IrG gbfrNYImu3s7y1Cfrc/KOqHPHZdMo5qKmJM3nSRzzKV4Thc+Fgmn3gHQWi0mzcbm5MHp DlsuY+qSL/ER/AiwgItnw+vybw87u4KCPGJvtsZcVH5SPtl1XQ5zB8vl1WzjCSWO39Ii MTS1ASsILQIpFk7n1ld7mIs/DY8nD97dEybWh151bPSDcQs4/hixizglUEUDgWtO3k/Z TAHwjvw7fROIICTTJVNiGXjURd1tw9HjfJvLvvx/G3hG5gH4t7lJ+gmuInlzePEYWNCA vV/w== X-Gm-Message-State: AOJu0YwnNLCWpAwFmpWU5Yn/oYfvy6uFEXD5s30g+SlAookdCko7IS+C Twjoxjq4Uy5WJJ++sHllfac1MawLuJUUZ7oDA4YpfMa649282I3spplN6P8LR0BWTRM2TcL9sDa r0g== X-Google-Smtp-Source: AGHT+IEdE+/dkCePTdsFNvInxRUqaZQvpfEuUzw6kpBRTizb35saxv9i1LRTSeJsBYMGOjqbW+KA5Q== X-Received: by 2002:a05:6402:210f:b0:5ce:add3:feaf with SMTP id 4fb4d7f45d1cf-5ceadd40012mr15751012a12.22.1730822454488; Tue, 05 Nov 2024 08:00:54 -0800 (PST) From: Phil Dennis-Jordan To: qemu-devel@nongnu.org Cc: dirty@apple.com, rbolshakov@ddn.com, pbonzini@redhat.com, Phil Dennis-Jordan Subject: [PATCH 1/5] i386/hvf: Integrates x2APIC support with hvf accel Date: Tue, 5 Nov 2024 16:57:56 +0100 Message-Id: <20241105155800.5461-2-phil@philjordan.eu> X-Mailer: git-send-email 2.39.3 (Apple Git-145) In-Reply-To: <20241105155800.5461-1-phil@philjordan.eu> References: <20241105155800.5461-1-phil@philjordan.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: neutral client-ip=2a00:1450:4864:20::52b; envelope-from=phil@philjordan.eu; helo=mail-ed1-x52b.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @philjordan-eu.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1730822506612116600 Support for x2APIC mode was recently introduced in the software emulated APIC implementation for TCG. Enabling it when using macOS=E2=80=99s hvf accelerator is useful and significantly helps performance, as Qemu currently uses the emulated APIC when running on hvf as well. This change wires up the read & write operations for the MSR VM exits and allow-lists the CPUID flag in the x86 hvf runtime. Signed-off-by: Phil Dennis-Jordan Reviewed-by: Roman Bolshakov --- v2: * Fixed merge conflict due to recent upstream CPUID code change. target/i386/hvf/x86_cpuid.c | 2 +- target/i386/hvf/x86_emu.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/target/i386/hvf/x86_cpuid.c b/target/i386/hvf/x86_cpuid.c index 3a116548a3d..ac922d7fd16 100644 --- a/target/i386/hvf/x86_cpuid.c +++ b/target/i386/hvf/x86_cpuid.c @@ -77,7 +77,7 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t = idx, ecx &=3D CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_MOVBE | - CPUID_EXT_POPCNT | CPUID_EXT_AES | + CPUID_EXT_POPCNT | CPUID_EXT_AES | CPUID_EXT_X2APIC | (supported_xcr0 ? CPUID_EXT_XSAVE : 0) | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND; ecx |=3D CPUID_EXT_HYPERVISOR; diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 38c782b8e3b..be675bcfb71 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -663,6 +663,15 @@ static void exec_lods(CPUX86State *env, struct x86_dec= ode *decode) env->eip +=3D decode->len; } =20 +static void raise_exception(CPUX86State *env, int exception_index, + int error_code) +{ + env->exception_nr =3D exception_index; + env->error_code =3D error_code; + env->has_error_code =3D true; + env->exception_injected =3D 1; +} + void simulate_rdmsr(CPUX86State *env) { X86CPU *cpu =3D env_archcpu(env); @@ -677,6 +686,17 @@ void simulate_rdmsr(CPUX86State *env) case MSR_IA32_APICBASE: val =3D cpu_get_apic_base(cpu->apic_state); break; + case MSR_APIC_START ... MSR_APIC_END: { + int ret; + int index =3D (uint32_t)env->regs[R_ECX] - MSR_APIC_START; + + ret =3D apic_msr_read(index, &val); + if (ret < 0) { + raise_exception(env, EXCP0D_GPF, 0); + } + + break; + } case MSR_IA32_UCODE_REV: val =3D cpu->ucode_rev; break; @@ -777,6 +797,17 @@ void simulate_wrmsr(CPUX86State *env) case MSR_IA32_APICBASE: cpu_set_apic_base(cpu->apic_state, data); break; + case MSR_APIC_START ... MSR_APIC_END: { + int ret; + int index =3D (uint32_t)env->regs[R_ECX] - MSR_APIC_START; + + ret =3D apic_msr_write(index, data); + if (ret < 0) { + raise_exception(env, EXCP0D_GPF, 0); + } + + break; + } case MSR_FSBASE: wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data); break; --=20 2.39.3 (Apple Git-145)