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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432a3688813sm16354555e9.1.2024.11.05.03.19.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Nov 2024 03:19:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1730805581; x=1731410381; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=1ITym5U3J9cuAVSZN3O87UN4hyjdbTQKA+1cJNNI3AY=; b=jG1AbU135apmnC9jNo7x6hgjx4jHgOryrRhYZZU8J3JY44+PV5x7799mCSILrrH3Bx +pjiyLZVAaG5I5XFsYfh3FK/3QHER25MLfFbPUuBOXKES3ScWzkNOP06pBpbGuoALK3C /XqX3WCafrS4uxSigiXkJJjrKmg2qESZ46PgeE2Q/8JkC8v6clpMzUXoU0WBAXA6Svlx xyHVzDms6Lg8ouwc2PgU4PfgQcnlS0hS9VIm3z86s2BvdJLDcgY5HNMt3RhtAjtm5YGM Ys7hJvOXoi8AicYvDIUuJfJZKw8oFheXb/p/AwJiM/+z1mVpE1RoTJ8T6tYBGbE+WSQ6 OOSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730805581; x=1731410381; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1ITym5U3J9cuAVSZN3O87UN4hyjdbTQKA+1cJNNI3AY=; b=nj21cBtpw0HTIpDiLXGAkEcMTvWFPwkFAH02zeOd5tJPp4bMRUTx5m5dPM0HEh8VZy tGGe0WQixX6n0Sx7mlDsw31Ec8NGVzd933yDr7pDPgUBwIIKX7F6epFf4Amg04S2qh0o 5bidHio0FAHwuypjrzAhV1/4d4keyFjPmNMV0TNa2TSXTpEffqJlt3Zk6mijzQDIpnbg ISrYbz/rY6jeFVA9g8IfKMKSf1RE+T3nXzyxOeyPYmBXEGfMM8BLiJa270s82hGHjSX3 kOjg95KTxsQG+SfYsag9cdIZwDR+oB6gjnM6zSfexcCiOfkcKm+0SPIvtbsM4uhtSwJC Cxmg== X-Gm-Message-State: AOJu0YxeHdqAho5RG+T92hQFmbTKf+IX0J6PmEi0hpsL3iTxe1oq/kpp QuRKg4koGL2MJR9jaEa6zYyUcEiYU4EcBaehnfuUpzFAGMn6Grk2LR5ij9XJcbpmW09SRMvZdwB T X-Google-Smtp-Source: AGHT+IEyWtuYGCcJmMHyDK6y4iMqyjX2LlXPkwkTB3/YbuwXCaXx+Ik6hVVqr/xMfNdQNRf6Kmh2vw== X-Received: by 2002:a05:600c:5486:b0:431:52cc:877a with SMTP id 5b1f17b1804b1-43283296066mr165633785e9.34.1730805581139; Tue, 05 Nov 2024 03:19:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/31] target/hppa: Explicitly set 2-NaN propagation rule Date: Tue, 5 Nov 2024 11:19:10 +0000 Message-Id: <20241105111935.2747034-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105111935.2747034-1-peter.maydell@linaro.org> References: <20241105111935.2747034-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730805671068116600 Content-Type: text/plain; charset="utf-8" Set the 2-NaN propagation rule explicitly in env->fp_status. Really we only need to do this at CPU reset (after reset has zeroed out most of the CPU state struct, which typically includes fp_status fields). However target/hppa does not currently implement CPU reset at all, so leave a TODO comment to note that this could be moved if we ever do implement reset. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241025141254.2141506-7-peter.maydell@linaro.org --- target/hppa/fpu_helper.c | 6 ++++++ fpu/softfloat-specialize.c.inc | 4 ++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index deaed2b65d1..0e44074ba82 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -49,6 +49,12 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) d =3D FIELD_EX32(shadow, FPSR, D); set_flush_to_zero(d, &env->fp_status); set_flush_inputs_to_zero(d, &env->fp_status); + + /* + * TODO: we only need to do this at CPU reset, but currently + * HPPA does note implement a CPU reset method at all... + */ + set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); } =20 void cpu_hppa_loaded_fr0(CPUHPPAState *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index bbc3b70fa9d..4e51cf8d083 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -403,9 +403,9 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, #if defined(TARGET_AVR) || defined(TARGET_HEXAGON) \ || defined(TARGET_RISCV) || defined(TARGET_SH4) \ || defined(TARGET_TRICORE) || defined(TARGET_ARM) || defined(TARGET_MI= PS) \ - || defined(TARGET_LOONGARCH64) + || defined(TARGET_LOONGARCH64) || defined(TARGET_HPPA) g_assert_not_reached(); -#elif defined(TARGET_HPPA) || defined(TARGET_S390X) +#elif defined(TARGET_S390X) rule =3D float_2nan_prop_s_ab; #elif defined(TARGET_PPC) || defined(TARGET_M68K) /* --=20 2.34.1