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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432a3688813sm16354555e9.1.2024.11.05.03.19.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Nov 2024 03:19:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1730805591; x=1731410391; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=FBJ7C4+ClTBlCUSOBe+gLo7sz1EnjPStvDm17hGVx2c=; b=izdKyItZepj/PE6PIHB6b5aO6fCmI8Smaa1yxLF2ous9gzF8zWIflmYUmywi/32tW5 0HtU1SCAsNNgoHch39zRquHNdha2Q+ZUdxXKSKSqa44zWqs++7voyQmBXn2MTTjOj9xU U1nHdaZMoZyXE6OgCAN4An2nschVXgjb+DVf/Xb/M0fnszIrKdM4S6xY4N8lGbrIJh0Q viE9OlCw8pQXbB1ifIRx6f4qhEdXA1H5krqsMe0s7gc/ehOPuq2k55llKDbh0FAJQC1J zWE8NMhjkLc/Nvle+WF2QUrLn+Lj6PwTbJ+uumKjTu3MQgetEkvxpsS7DS/+RA/uAM3H LmEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730805591; x=1731410391; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FBJ7C4+ClTBlCUSOBe+gLo7sz1EnjPStvDm17hGVx2c=; b=ocEq19ErcDRTCn6vHLfgFmO+Sv9zWSCBRw0cxpr9qQRDAbebVG3D+u00YQ9xWtfuzI HmAc+HV/QWeRI4jsNyePaAKgZWsJ8DVfwbzlSBwmnWzQ6E54db9HD6ioNP0jZU8k9WuH M/jYddYzX7ss1Fa2+3Rlr3ZNv3drQsQtmDYR+En7noAHDb9RD29Rae08i5s0/P4d2ini DRer2dPa26/XUqzeFAN/otFX8FjYPEjPx5+jMHxdNWvr+YDsTpxEZl4l9HtRd7FqBBBk 4KcHkyNcivfoySbSMOsGTusfWoUZEo4ju0sm6mEJc1X7y+J7w3/nSaARDbeNHutW6ty3 Wx5A== X-Gm-Message-State: AOJu0YzUWCZZc1tvXMHwDhbQ86EM+kuUph6waQdFllkWIHmeEZaXjTRv HVrqp+S5Qy/iDNj61AzjximQ43fqELy4KE2Yp+M2mm0ekE4LM+Hhhq6zPCSuBLVNqZF6JZLPA4p a X-Google-Smtp-Source: AGHT+IFhXyu+hyXj6A5Fxf5mjkvhfCpgRVojTyQ10HTgI6jCTXxofr97SSuvS18BsOUgHRMxVhgKuQ== X-Received: by 2002:a05:6512:1193:b0:539:e436:f1cc with SMTP id 2adb3069b0e04-53d65e264e8mr7159660e87.52.1730805591459; Tue, 05 Nov 2024 03:19:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/31] target/arm: Fix SVE SDOT/UDOT/USDOT (4-way, indexed) Date: Tue, 5 Nov 2024 11:19:28 +0000 Message-Id: <20241105111935.2747034-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105111935.2747034-1-peter.maydell@linaro.org> References: <20241105111935.2747034-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730805872059116600 Content-Type: text/plain; charset="utf-8" Our implementation of the indexed version of SVE SDOT/UDOT/USDOT got the calculation of the inner loop terminator wrong. Although we correctly account for the element size when we calculate the terminator for the first iteration: intptr_t segend =3D MIN(16 / sizeof(TYPED), opr_sz_n); we don't do that when we move it forward after the first inner loop completes. The intention is that we process the vector in 128-bit segments, which for a 64-bit element size should mean (1, 2), (3, 4), (5, 6), etc. This bug meant that we would iterate (1, 2), (3, 4, 5, 6), (7, 8, 9, 10) etc and apply the wrong indexed element to some of the operations, and also index off the end of the vector. You don't see this bug if the vector length is small enough that we don't need to iterate the outer loop, i.e. if it is only 128 bits, or if it is the 64-bit special case from AA32/AA64 AdvSIMD. If the vector length is 256 bits then we calculate the right results for the elements in the vector but do index off the end of the vector. Vector lengths greater than 256 bits see wrong answers. The instructions that produce 32-bit results behave correctly. Fix the recalculation of 'segend' for subsequent iterations, and restore a version of the comment that was lost in the refactor of commit 7020ffd656a5 that explains why we only need to clamp segend to opr_sz_n for the first iteration, not the later ones. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2595 Fixes: 7020ffd656a5 ("target/arm: Macroize helper_gvec_{s,u}dot_idx_{b,h}") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241101185544.2130972-1-peter.maydell@linaro.org --- target/arm/tcg/vec_helper.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 22ddb968817..e825d501a22 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -836,6 +836,13 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void *= va, uint32_t desc) \ { \ intptr_t i =3D 0, opr_sz =3D simd_oprsz(desc); = \ intptr_t opr_sz_n =3D opr_sz / sizeof(TYPED); = \ + /* \ + * Special case: opr_sz =3D=3D 8 from AA64/AA32 advsimd means the = \ + * first iteration might not be a full 16 byte segment. But \ + * for vector lengths beyond that this must be SVE and we know \ + * opr_sz is a multiple of 16, so we need not clamp segend \ + * to opr_sz_n when we advance it at the end of the loop. \ + */ \ intptr_t segend =3D MIN(16 / sizeof(TYPED), opr_sz_n); = \ intptr_t index =3D simd_data(desc); = \ TYPED *d =3D vd, *a =3D va; = \ @@ -853,7 +860,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void *v= a, uint32_t desc) \ n[i * 4 + 2] * m2 + \ n[i * 4 + 3] * m3); \ } while (++i < segend); \ - segend =3D i + 4; = \ + segend =3D i + (16 / sizeof(TYPED)); = \ } while (i < opr_sz_n); \ clear_tail(d, opr_sz, simd_maxsz(desc)); \ } --=20 2.34.1