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Tsirkin" , Marcel Apfelbaum , Igor Mammedov , Ani Sinha Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Cornelia Huck , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Eric Blake , Markus Armbruster , Marcelo Tosatti , rick.p.edgecombe@intel.com, kvm@vger.kernel.org, qemu-devel@nongnu.org, xiaoyao.li@intel.com Subject: [PATCH v6 46/60] i386/cgs: Rename *mask_cpuid_features() to *adjust_cpuid_features() Date: Tue, 5 Nov 2024 01:23:54 -0500 Message-Id: <20241105062408.3533704-47-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105062408.3533704-1-xiaoyao.li@intel.com> References: <20241105062408.3533704-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.18; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -39 X-Spam_score: -4.0 X-Spam_bar: ---- X-Spam_report: (-4.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.781, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730788971967116600 Content-Type: text/plain; charset="utf-8" Because for TDX case, there are also fixed-1 bits that enfored by TDX module. Signed-off-by: Xiaoyao Li --- target/i386/confidential-guest.h | 20 ++++++++++---------- target/i386/kvm/kvm.c | 2 +- target/i386/sev.c | 4 ++-- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/target/i386/confidential-guest.h b/target/i386/confidential-gu= est.h index 4b7ea91023dc..2dde29889c23 100644 --- a/target/i386/confidential-guest.h +++ b/target/i386/confidential-guest.h @@ -41,8 +41,8 @@ struct X86ConfidentialGuestClass { int (*kvm_type)(X86ConfidentialGuest *cg); void (*cpu_instance_init)(X86ConfidentialGuest *cg, CPUState *cpu); void (*cpu_realizefn)(X86ConfidentialGuest *cg, CPUState *cpu, Error *= *errp); - uint32_t (*mask_cpuid_features)(X86ConfidentialGuest *cg, uint32_t fea= ture, uint32_t index, - int reg, uint32_t value); + uint32_t (*adjust_cpuid_features)(X86ConfidentialGuest *cg, uint32_t f= eature, + uint32_t index, int reg, uint32_t va= lue); }; =20 /** @@ -83,21 +83,21 @@ static inline void x86_confidenetial_guest_cpu_realizef= n(X86ConfidentialGuest *c } =20 /** - * x86_confidential_guest_mask_cpuid_features: + * x86_confidential_guest_adjust_cpuid_features: * - * Removes unsupported features from a confidential guest's CPUID values, = returns - * the value with the bits removed. The bits removed should be those that= KVM - * provides independent of host-supported CPUID features, but are not supp= orted by - * the confidential computing firmware. + * Adjust the supported features from a confidential guest's CPUID values, + * returns the adjusted value. There are bits being removed that are not + * supported by the confidential computing firmware or bits being added th= at + * are forcibly exposed to guest by the confidential computing firmware. */ -static inline int x86_confidential_guest_mask_cpuid_features(X86Confidenti= alGuest *cg, +static inline int x86_confidential_guest_adjust_cpuid_features(X86Confiden= tialGuest *cg, uint32_t feat= ure, uint32_t index, int reg, uint= 32_t value) { X86ConfidentialGuestClass *klass =3D X86_CONFIDENTIAL_GUEST_GET_CLASS(= cg); =20 - if (klass->mask_cpuid_features) { - return klass->mask_cpuid_features(cg, feature, index, reg, value); + if (klass->adjust_cpuid_features) { + return klass->adjust_cpuid_features(cg, feature, index, reg, value= ); } else { return value; } diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index e47aa32233e6..f067961fba43 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -576,7 +576,7 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint= 32_t function, } =20 if (current_machine->cgs) { - ret =3D x86_confidential_guest_mask_cpuid_features( + ret =3D x86_confidential_guest_adjust_cpuid_features( X86_CONFIDENTIAL_GUEST(current_machine->cgs), function, index, reg, ret); } diff --git a/target/i386/sev.c b/target/i386/sev.c index 1a4eb1ada624..4e6582c6a666 100644 --- a/target/i386/sev.c +++ b/target/i386/sev.c @@ -946,7 +946,7 @@ out: } =20 static uint32_t -sev_snp_mask_cpuid_features(X86ConfidentialGuest *cg, uint32_t feature, ui= nt32_t index, +sev_snp_adjust_cpuid_features(X86ConfidentialGuest *cg, uint32_t feature, = uint32_t index, int reg, uint32_t value) { switch (feature) { @@ -2404,7 +2404,7 @@ sev_snp_guest_class_init(ObjectClass *oc, void *data) klass->launch_finish =3D sev_snp_launch_finish; klass->launch_update_data =3D sev_snp_launch_update_data; klass->kvm_init =3D sev_snp_kvm_init; - x86_klass->mask_cpuid_features =3D sev_snp_mask_cpuid_features; + x86_klass->adjust_cpuid_features =3D sev_snp_adjust_cpuid_features; x86_klass->kvm_type =3D sev_snp_kvm_type; =20 object_class_property_add(oc, "policy", "uint64", --=20 2.34.1