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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=202.12.124.156; envelope-from=its@irrelevant.dk; helo=fhigh-b5-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @irrelevant.dk) X-ZM-MESSAGEID: 1730744088986116600 Content-Type: text/plain; charset="utf-8" From: Ayush Mishra Add the NPDGL and NPDAL fields to support large alignment and granularities. Signed-off-by: Ayush Mishra Reviewed-by: Klaus Jensen Link: https://lore.kernel.org/r/20241001012833.3551820-1-ayush.m55@samsung.= com [k.jensen: renamed the enum values] Signed-off-by: Klaus Jensen --- hw/nvme/ns.c | 5 ++++- include/block/nvme.h | 17 ++++++++++++++++- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/hw/nvme/ns.c b/hw/nvme/ns.c index 6dbdcb49bfc1..526e15aa8018 100644 --- a/hw/nvme/ns.c +++ b/hw/nvme/ns.c @@ -30,6 +30,7 @@ void nvme_ns_init_format(NvmeNamespace *ns) { NvmeIdNs *id_ns =3D &ns->id_ns; + NvmeIdNsNvm *id_ns_nvm =3D &ns->id_ns_nvm; BlockDriverInfo bdi; int npdg, ret; int64_t nlbas; @@ -55,6 +56,8 @@ void nvme_ns_init_format(NvmeNamespace *ns) } =20 id_ns->npda =3D id_ns->npdg =3D npdg - 1; + id_ns_nvm->npdal =3D npdg; + id_ns_nvm->npdgl =3D npdg; } =20 static int nvme_ns_init(NvmeNamespace *ns, Error **errp) @@ -73,7 +76,7 @@ static int nvme_ns_init(NvmeNamespace *ns, Error **errp) ns->id_ns.dlfeat =3D 0x1; =20 /* support DULBE and I/O optimization fields */ - id_ns->nsfeat |=3D (0x4 | 0x10); + id_ns->nsfeat |=3D (NVME_ID_NS_NSFEAT_DAE | NVME_ID_NS_NSFEAT_OPTPERF_= ALL); =20 if (ns->params.shared) { id_ns->nmic |=3D NVME_ID_NS_IND_NMIC_SHRNS; diff --git a/include/block/nvme.h b/include/block/nvme.h index 39955a63455f..f4d108841bf5 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -1418,7 +1418,12 @@ typedef struct QEMU_PACKED NvmeIdNsNvm { uint8_t pic; uint8_t rsvd9[3]; uint32_t elbaf[NVME_MAX_NLBAF]; - uint8_t rsvd268[3828]; + uint32_t npdgl; + uint32_t nprg; + uint32_t npra; + uint32_t nors; + uint32_t npdal; + uint8_t rsvd288[3808]; } NvmeIdNsNvm; =20 typedef struct QEMU_PACKED NvmeIdNsInd { @@ -1536,6 +1541,16 @@ enum NvmeIdNsMc { NVME_ID_NS_MC_SEPARATE =3D 1 << 1, }; =20 +enum NvmeIdNsNsfeat { + NVME_ID_NS_NSFEAT_THINP =3D 1 << 0, + NVME_ID_NS_NSFEAT_NSABPNS =3D 1 << 1, + NVME_ID_NS_NSFEAT_DAE =3D 1 << 2, + NVME_ID_NS_NSFEAT_UIDREUSE =3D 1 << 3, + NVME_ID_NS_NSFEAT_OPTPERF_ALL =3D 3 << 4, + NVME_ID_NS_NSFEAT_MAM =3D 1 << 6, + NVME_ID_NS_NSFEAT_OPTRPERF =3D 1 << 7, +}; + #define NVME_ID_NS_DPS_TYPE(dps) (dps & NVME_ID_NS_DPS_TYPE_MASK) =20 enum NvmePIFormat { --=20 2.45.2