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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=202.12.124.145; envelope-from=its@irrelevant.dk; helo=fout-b2-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @irrelevant.dk) X-ZM-MESSAGEID: 1730744100763116600 Content-Type: text/plain; charset="utf-8" From: Arun Kumar Add support for the I/O Command Set Independent Namespace Data Structure (CNS 8h and 1fh). Signed-off-by: Arun Kumar Reviewed-by: Klaus Jensen Link: https://lore.kernel.org/r/20240925004407.3521406-1-arun.kka@samsung.c= om Signed-off-by: Klaus Jensen --- hw/nvme/ctrl.c | 31 +++++++++++++++++++++++++++++++ hw/nvme/ns.c | 6 +++++- hw/nvme/nvme.h | 1 + hw/nvme/trace-events | 1 + include/block/nvme.h | 23 +++++++++++++++++++++-- 5 files changed, 59 insertions(+), 3 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index f4e89203c1a6..8e4612e03567 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -5692,6 +5692,33 @@ static uint16_t nvme_identify_sec_ctrl_list(NvmeCtrl= *n, NvmeRequest *req) return nvme_c2h(n, (uint8_t *)&list, sizeof(list), req); } =20 +static uint16_t nvme_identify_ns_ind(NvmeCtrl *n, NvmeRequest *req, bool a= lloc) +{ + NvmeNamespace *ns; + NvmeIdentify *c =3D (NvmeIdentify *)&req->cmd; + uint32_t nsid =3D le32_to_cpu(c->nsid); + + trace_pci_nvme_identify_ns_ind(nsid); + + if (!nvme_nsid_valid(n, nsid) || nsid =3D=3D NVME_NSID_BROADCAST) { + return NVME_INVALID_NSID | NVME_DNR; + } + + ns =3D nvme_ns(n, nsid); + if (unlikely(!ns)) { + if (alloc) { + ns =3D nvme_subsys_ns(n->subsys, nsid); + if (!ns) { + return nvme_rpt_empty_id_struct(n, req); + } + } else { + return nvme_rpt_empty_id_struct(n, req); + } + } + + return nvme_c2h(n, (uint8_t *)&ns->id_ns_ind, sizeof(NvmeIdNsInd), req= ); +} + static uint16_t nvme_identify_ns_csi(NvmeCtrl *n, NvmeRequest *req, bool active) { @@ -5946,6 +5973,10 @@ static uint16_t nvme_identify(NvmeCtrl *n, NvmeReque= st *req) return nvme_identify_sec_ctrl_list(n, req); case NVME_ID_CNS_CS_NS: return nvme_identify_ns_csi(n, req, true); + case NVME_ID_CNS_CS_IND_NS: + return nvme_identify_ns_ind(n, req, false); + case NVME_ID_CNS_CS_IND_NS_ALLOCATED: + return nvme_identify_ns_ind(n, req, true); case NVME_ID_CNS_CS_NS_PRESENT: return nvme_identify_ns_csi(n, req, false); case NVME_ID_CNS_CTRL: diff --git a/hw/nvme/ns.c b/hw/nvme/ns.c index ea8db175dbd1..6dbdcb49bfc1 100644 --- a/hw/nvme/ns.c +++ b/hw/nvme/ns.c @@ -62,6 +62,7 @@ static int nvme_ns_init(NvmeNamespace *ns, Error **errp) static uint64_t ns_count; NvmeIdNs *id_ns =3D &ns->id_ns; NvmeIdNsNvm *id_ns_nvm =3D &ns->id_ns_nvm; + NvmeIdNsInd *id_ns_ind =3D &ns->id_ns_ind; uint8_t ds; uint16_t ms; int i; @@ -75,7 +76,9 @@ static int nvme_ns_init(NvmeNamespace *ns, Error **errp) id_ns->nsfeat |=3D (0x4 | 0x10); =20 if (ns->params.shared) { - id_ns->nmic |=3D NVME_NMIC_NS_SHARED; + id_ns->nmic |=3D NVME_ID_NS_IND_NMIC_SHRNS; + id_ns_ind->nmic =3D NVME_ID_NS_IND_NMIC_SHRNS; + id_ns_ind->nstat =3D NVME_ID_NS_IND_NSTAT_NRDY; } =20 /* Substitute a missing EUI-64 by an autogenerated one */ @@ -770,6 +773,7 @@ static void nvme_ns_realize(DeviceState *dev, Error **e= rrp) subsys->namespaces[nsid] =3D ns; =20 ns->id_ns.endgid =3D cpu_to_le16(0x1); + ns->id_ns_ind.endgrpid =3D cpu_to_le16(0x1); =20 if (ns->params.detached) { return; diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index 7566b316d12d..724220691057 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -233,6 +233,7 @@ typedef struct NvmeNamespace { int64_t moff; NvmeIdNs id_ns; NvmeIdNsNvm id_ns_nvm; + NvmeIdNsInd id_ns_ind; NvmeLBAF lbaf; unsigned int nlbaf; size_t lbasz; diff --git a/hw/nvme/trace-events b/hw/nvme/trace-events index 3a67680c6ad1..6be0bfa1c1fc 100644 --- a/hw/nvme/trace-events +++ b/hw/nvme/trace-events @@ -56,6 +56,7 @@ pci_nvme_identify(uint16_t cid, uint8_t cns, uint16_t ctr= lid, uint8_t csi) "cid pci_nvme_identify_ctrl(void) "identify controller" pci_nvme_identify_ctrl_csi(uint8_t csi) "identify controller, csi=3D0x%"PR= Ix8"" pci_nvme_identify_ns(uint32_t ns) "nsid %"PRIu32"" +pci_nvme_identify_ns_ind(uint32_t nsid) "nsid %"PRIu32"" pci_nvme_identify_ctrl_list(uint8_t cns, uint16_t cntid) "cns 0x%"PRIx8" c= ntid %"PRIu16"" pci_nvme_identify_pri_ctrl_cap(uint16_t cntlid) "identify primary controll= er capabilities cntlid=3D%"PRIu16"" pci_nvme_identify_sec_ctrl_list(uint16_t cntlid, uint8_t numcntl) "identif= y secondary controller list cntlid=3D%"PRIu16" numcntl=3D%"PRIu8"" diff --git a/include/block/nvme.h b/include/block/nvme.h index a37be0d0da8e..39955a63455f 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -1077,6 +1077,7 @@ enum NvmeIdCns { NVME_ID_CNS_CS_NS =3D 0x05, NVME_ID_CNS_CS_CTRL =3D 0x06, NVME_ID_CNS_CS_NS_ACTIVE_LIST =3D 0x07, + NVME_ID_CNS_CS_IND_NS =3D 0x08, NVME_ID_CNS_NS_PRESENT_LIST =3D 0x10, NVME_ID_CNS_NS_PRESENT =3D 0x11, NVME_ID_CNS_NS_ATTACHED_CTRL_LIST =3D 0x12, @@ -1087,6 +1088,7 @@ enum NvmeIdCns { NVME_ID_CNS_CS_NS_PRESENT_LIST =3D 0x1a, NVME_ID_CNS_CS_NS_PRESENT =3D 0x1b, NVME_ID_CNS_IO_COMMAND_SET =3D 0x1c, + NVME_ID_CNS_CS_IND_NS_ALLOCATED =3D 0x1f, }; =20 typedef struct QEMU_PACKED NvmeIdCtrl { @@ -1419,6 +1421,20 @@ typedef struct QEMU_PACKED NvmeIdNsNvm { uint8_t rsvd268[3828]; } NvmeIdNsNvm; =20 +typedef struct QEMU_PACKED NvmeIdNsInd { + uint8_t nsfeat; + uint8_t nmic; + uint8_t rescap; + uint8_t fpi; + uint32_t anagrpid; + uint8_t nsattr; + uint8_t rsvd9; + uint16_t nvmsetid; + uint16_t endgrpid; + uint8_t nstat; + uint8_t rsvd15[4081]; +} NvmeIdNsInd; + typedef struct QEMU_PACKED NvmeIdNsDescr { uint8_t nidt; uint8_t nidl; @@ -1439,8 +1455,10 @@ enum NvmeNsIdentifierType { NVME_NIDT_CSI =3D 0x04, }; =20 -enum NvmeIdNsNmic { - NVME_NMIC_NS_SHARED =3D 1 << 0, +enum NvmeIdNsIndependent { + NVME_ID_NS_IND_NMIC_SHRNS =3D 1 << 0, + NVME_ID_NS_IND_NMIC_DISNS =3D 1 << 1, + NVME_ID_NS_IND_NSTAT_NRDY =3D 1 << 0, }; =20 enum NvmeCsi { @@ -1873,6 +1891,7 @@ static inline void _nvme_check_size(void) QEMU_BUILD_BUG_ON(sizeof(NvmeLBAF) !=3D 4); QEMU_BUILD_BUG_ON(sizeof(NvmeLBAFE) !=3D 16); QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) !=3D 4096); + QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsInd) !=3D 4096); QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsNvm) !=3D 4096); QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsZoned) !=3D 4096); QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) !=3D 16); --=20 2.45.2