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([152.234.121.56]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-720bc20e4c2sm7550953b3a.91.2024.11.04.04.38.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2024 04:38:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1730723929; x=1731328729; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=98jwi9p0o8fOmk8UPM/sqRh+geOrtT788L2sLhtj3/o=; b=G5JIHuikYGh0vMLkut5DV3dGmGYpr01oEteH5elZ6nexl6/zy/eamzrKykjZ7s3nqz vdeNXOLmu+FqN55h/++r/+8ngDj23xuAlmT92ZdfLeLOdzFrpHmzHpr2o7stE3xoYLJq j05U5sKdY2uS/1ojnm9qY1XTjFbf5xdBgdg1CL1kKM3x0qaS2x3XoZkYh4u+CJRE4uVd MVjO+X88wg68j6oc14MaIXMX53t7VOea+o1K1TrJomgtXwml7Q/YDMIvsGQYbj4AowVe ktBSBw/74S/e9jirselnVqZg/X6E2MA4ScKj9iRMyosRPWaiCJTl3NYAIowMX/jVUhuv P+9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730723929; x=1731328729; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=98jwi9p0o8fOmk8UPM/sqRh+geOrtT788L2sLhtj3/o=; b=YjDMaDo+cCZRVmymTSQUwW1B19PsiUqF9G37UBD5Wcu22HI3YYbNEUy5BNVj0iId6W pHPqa0X7jzBpPRr/RxBFDqHrd0hEu5i3PXCNihHWbmWupZzXj6fKtvkHPXCo6i375VGS HAJ4ll3kS1PUSQ5eaoFT3rVbMrr5HScVZdj4FOsB+XlPRSANmwdRY1XDe0YDCzIXs9Ko zCa+g+PUnUX9QPt7rJjR7aCtxspZ0gZBA1MaQ1QJ8IzPF3cX+aRvxSvPlD2zZbxZjRYQ aAtIgrvw2yzF70c5KXGa6iT0TEWk3qp4c01Jh+AmA/u0RUBuyLBsv5wtGhXx78mLD2Q9 4uUg== X-Gm-Message-State: AOJu0YyoExoZuWwqRUK9b9cvBP3Ae8jFLUMzWw6ejHoVxpOUbCK0E7J1 cHppH8p8igXOPUm93FvfuYXTeMiQccddH3cuCQL/IOuwW/61bHHCt2OPxC+jDHIWDQ99qzFnUqn W X-Google-Smtp-Source: AGHT+IFKu7hqEN439YF4lNoCIO/jofqVEb5OHNN68TMEEivr50e8YKHlJgQl8U1e8nNiVEl2M4OeVw== X-Received: by 2002:a05:6a20:7483:b0:1db:e5ac:3d5b with SMTP id adf61e73a8af0-1dbe5ac3d81mr1616634637.39.1730723928668; Mon, 04 Nov 2024 04:38:48 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, peter.maydell@linaro.org, Daniel Henrique Barboza Subject: [PATCH 1/2] hw/riscv/riscv-iommu: change 'depth' to int Date: Mon, 4 Nov 2024 09:38:38 -0300 Message-ID: <20241104123839.533442-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104123839.533442-1-dbarboza@ventanamicro.com> References: <20241104123839.533442-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1730724035177116600 Content-Type: text/plain; charset="utf-8" Coverity reports an unsigned overflow when doing: for (; depth-- > 0; ) { When depth =3D 0 inside riscv_iommu_ctx_fetch(). Building it with a recent GCC the code doesn't actually break with depth =3D 0, i.e. the comparison "0-- > 0" will exit the loop instead of proceeding, but 'depth' will retain the overflow value afterwards. This behavior can be compiler dependent, so change 'depth' to int to remove this potential ambiguity. Resolves: Coverity CID 1564783 Fixes: 0c54acb8243 ("hw/riscv: add RISC-V IOMMU base emulation") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/riscv-iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index feb650549a..05341ad20b 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -846,7 +846,7 @@ static int riscv_iommu_ctx_fetch(RISCVIOMMUState *s, RI= SCVIOMMUContext *ctx) /* Device Context format: 0: extended (64 bytes) | 1: base (32 bytes) = */ const int dc_fmt =3D !s->enable_msi; const size_t dc_len =3D sizeof(dc) >> dc_fmt; - unsigned depth; + int depth; uint64_t de; =20 switch (mode) { --=20 2.45.2