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Mon, 04 Nov 2024 02:53:07 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 08/14] target/mips: Convert Loongson [D]DIVU.G opcodes to decodetree Date: Mon, 4 Nov 2024 11:52:47 +0100 Message-ID: <20241104105250.57818-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104105250.57818-1-philmd@linaro.org> References: <20241104105250.57818-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730717615141116600 From: Philippe Mathieu-Daud=C3=A9 Convert DIVU.G (divide 32-bit unsigned integers) and DDIVU.G (divide 64-bit unsigned integers) opcodes to decodetree. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20241026175349.84523-7-philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/godson2.decode | 2 ++ target/mips/tcg/loong-ext.decode | 2 ++ target/mips/tcg/loong_translate.c | 54 +++++++++++++++++++++++++++++++ target/mips/tcg/translate.c | 37 --------------------- 4 files changed, 58 insertions(+), 37 deletions(-) diff --git a/target/mips/tcg/godson2.decode b/target/mips/tcg/godson2.decode index cbf24ed88da..581cb9c8608 100644 --- a/target/mips/tcg/godson2.decode +++ b/target/mips/tcg/godson2.decode @@ -14,4 +14,6 @@ @rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv =20 DIV_G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd +DIVU_G 011111 ..... ..... ..... 00000 011011 @rs_rt_rd DDIV_G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd +DDIVU_G 011111 ..... ..... ..... 00000 011111 @rs_rt_rd diff --git a/target/mips/tcg/loong-ext.decode b/target/mips/tcg/loong-ext.d= ecode index 9397606beb6..e222167af56 100644 --- a/target/mips/tcg/loong-ext.decode +++ b/target/mips/tcg/loong-ext.decode @@ -16,3 +16,5 @@ =20 DIV_G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd +DIVU_G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd +DDIVU_G 011100 ..... ..... ..... 00000 010111 @rs_rt_rd diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_tran= slate.c index cb42acbdca4..2484b8a68df 100644 --- a/target/mips/tcg/loong_translate.c +++ b/target/mips/tcg/loong_translate.c @@ -87,6 +87,60 @@ static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a) return gen_lext_DIV_G(s, a->rd, a->rs, a->rt, true); } =20 +static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt, + bool is_double) +{ + TCGv t0, t1; + TCGLabel *l1, *l2; + + if (is_double) { + if (TARGET_LONG_BITS !=3D 64) { + return false; + } + check_mips_64(s); + } + + if (rd =3D=3D 0) { + /* Treat as NOP. */ + return true; + } + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + l1 =3D gen_new_label(); + l2 =3D gen_new_label(); + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + + if (!is_double) { + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + } + tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); + tcg_gen_movi_tl(cpu_gpr[rd], 0); + + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); + if (!is_double) { + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + } + gen_set_label(l2); + + return true; +} + +static bool trans_DIVU_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_DIVU_G(s, a->rd, a->rs, a->rt, false); +} + +static bool trans_DDIVU_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_DIVU_G(s, a->rd, a->rs, a->rt, true); +} + bool decode_ext_loongson(DisasContext *ctx, uint32_t insn) { if (!decode_64bit_enabled(ctx)) { diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 1c38e893d31..53bbbb761f8 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -332,8 +332,6 @@ enum { OPC_DMULT_G_2F =3D 0x11 | OPC_SPECIAL2, OPC_MULTU_G_2F =3D 0x12 | OPC_SPECIAL2, OPC_DMULTU_G_2F =3D 0x13 | OPC_SPECIAL2, - OPC_DIVU_G_2F =3D 0x16 | OPC_SPECIAL2, - OPC_DDIVU_G_2F =3D 0x17 | OPC_SPECIAL2, OPC_MOD_G_2F =3D 0x1c | OPC_SPECIAL2, OPC_DMOD_G_2F =3D 0x1d | OPC_SPECIAL2, OPC_MODU_G_2F =3D 0x1e | OPC_SPECIAL2, @@ -369,10 +367,8 @@ enum { /* Loongson 2E */ OPC_MULT_G_2E =3D 0x18 | OPC_SPECIAL3, OPC_MULTU_G_2E =3D 0x19 | OPC_SPECIAL3, - OPC_DIVU_G_2E =3D 0x1B | OPC_SPECIAL3, OPC_DMULT_G_2E =3D 0x1C | OPC_SPECIAL3, OPC_DMULTU_G_2E =3D 0x1D | OPC_SPECIAL3, - OPC_DDIVU_G_2E =3D 0x1F | OPC_SPECIAL3, OPC_MOD_G_2E =3D 0x22 | OPC_SPECIAL3, OPC_MODU_G_2E =3D 0x23 | OPC_SPECIAL3, OPC_DMOD_G_2E =3D 0x26 | OPC_SPECIAL3, @@ -3611,22 +3607,6 @@ static void gen_loongson_integer(DisasContext *ctx, = uint32_t opc, tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); break; - case OPC_DIVU_G_2E: - case OPC_DIVU_G_2F: - { - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - tcg_gen_ext32u_tl(t0, t0); - tcg_gen_ext32u_tl(t1, t1); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - gen_set_label(l2); - } - break; case OPC_MOD_G_2E: case OPC_MOD_G_2F: { @@ -3672,19 +3652,6 @@ static void gen_loongson_integer(DisasContext *ctx, = uint32_t opc, case OPC_DMULTU_G_2F: tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); break; - case OPC_DDIVU_G_2E: - case OPC_DDIVU_G_2F: - { - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); - gen_set_label(l2); - } - break; case OPC_DMOD_G_2E: case OPC_DMOD_G_2F: { @@ -13574,7 +13541,6 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) case OPC_MUL: gen_arith(ctx, op1, rd, rs, rt); break; - case OPC_DIVU_G_2F: case OPC_MULT_G_2F: case OPC_MULTU_G_2F: case OPC_MOD_G_2F: @@ -13608,7 +13574,6 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) break; case OPC_DMULT_G_2F: case OPC_DMULTU_G_2F: - case OPC_DDIVU_G_2F: case OPC_DMOD_G_2F: case OPC_DMODU_G_2F: check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); @@ -13746,7 +13711,6 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) =20 op1 =3D MASK_SPECIAL3(ctx->opcode); switch (op1) { - case OPC_DIVU_G_2E: case OPC_MOD_G_2E: case OPC_MODU_G_2E: case OPC_MULT_G_2E: @@ -14013,7 +13977,6 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) } break; #if defined(TARGET_MIPS64) - case OPC_DDIVU_G_2E: case OPC_DMULT_G_2E: case OPC_DMULTU_G_2E: case OPC_DMOD_G_2E: --=20 2.45.2