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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1730715329; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BZdvH/GfNWMkDbJPcCePcYhrbzcwgt3JfPMq8q8/Fw4=; b=VrNlEtaO5asGWdHTMKRJExEUYsqutRvlyfxCBTO7Q/KaTyGmkzqDZC1qko7LiSh/WYxQE5 m7M5+zsENQoN7PnLLmBPBx6a6Th2G+zm1kQqWB4BJ+ISoiEzderj2jeLJSjN7wD+tyC23a Y3BhF4/tfsjuaeDcl/eWW1bft4r6w4o= X-MC-Unique: YpOLog55PROVv3s6QsUvaQ-1 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 08/10] hw/sd/aspeed_sdhci: Introduce Capabilities Register 2 for SD slot 0 and 1 Date: Mon, 4 Nov 2024 11:14:59 +0100 Message-ID: <20241104101501.2487001-9-clg@redhat.com> In-Reply-To: <20241104101501.2487001-1-clg@redhat.com> References: <20241104101501.2487001-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1730715439890116600 From: Jamin Lin The size of SDHCI capabilities register is 64bits, so introduces new Capabilities Register 2 for SD slot 0 (0x144) and SD slot1 (0x244). Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater [ clg: Fixed code alignment ] Signed-off-by: C=C3=A9dric Le Goater --- hw/sd/aspeed_sdhci.c | 40 +++++++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 11 deletions(-) diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c index 427e5336a8fb..98d5460905df 100644 --- a/hw/sd/aspeed_sdhci.c +++ b/hw/sd/aspeed_sdhci.c @@ -24,8 +24,10 @@ #define ASPEED_SDHCI_DEBOUNCE_RESET 0x00000005 #define ASPEED_SDHCI_BUS 0x08 #define ASPEED_SDHCI_SDIO_140 0x10 +#define ASPEED_SDHCI_SDIO_144 0x14 #define ASPEED_SDHCI_SDIO_148 0x18 #define ASPEED_SDHCI_SDIO_240 0x20 +#define ASPEED_SDHCI_SDIO_244 0x24 #define ASPEED_SDHCI_SDIO_248 0x28 #define ASPEED_SDHCI_WP_POL 0xec #define ASPEED_SDHCI_CARD_DET 0xf0 @@ -35,21 +37,27 @@ =20 static uint64_t aspeed_sdhci_read(void *opaque, hwaddr addr, unsigned int = size) { - uint32_t val =3D 0; + uint64_t val =3D 0; AspeedSDHCIState *sdhci =3D opaque; =20 switch (addr) { case ASPEED_SDHCI_SDIO_140: - val =3D (uint32_t)sdhci->slots[0].capareg; + val =3D extract64(sdhci->slots[0].capareg, 0, 32); + break; + case ASPEED_SDHCI_SDIO_144: + val =3D extract64(sdhci->slots[0].capareg, 32, 32); break; case ASPEED_SDHCI_SDIO_148: - val =3D (uint32_t)sdhci->slots[0].maxcurr; + val =3D extract64(sdhci->slots[0].maxcurr, 0, 32); break; case ASPEED_SDHCI_SDIO_240: - val =3D (uint32_t)sdhci->slots[1].capareg; + val =3D extract64(sdhci->slots[1].capareg, 0, 32); + break; + case ASPEED_SDHCI_SDIO_244: + val =3D extract64(sdhci->slots[1].capareg, 32, 32); break; case ASPEED_SDHCI_SDIO_248: - val =3D (uint32_t)sdhci->slots[1].maxcurr; + val =3D extract64(sdhci->slots[1].maxcurr, 0, 32); break; default: if (addr < ASPEED_SDHCI_REG_SIZE) { @@ -61,9 +69,9 @@ static uint64_t aspeed_sdhci_read(void *opaque, hwaddr ad= dr, unsigned int size) } } =20 - trace_aspeed_sdhci_read(addr, size, (uint64_t) val); + trace_aspeed_sdhci_read(addr, size, val); =20 - return (uint64_t)val; + return val; } =20 static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val, @@ -79,16 +87,26 @@ static void aspeed_sdhci_write(void *opaque, hwaddr add= r, uint64_t val, sdhci->regs[TO_REG(addr)] =3D (uint32_t)val & ~ASPEED_SDHCI_INFO_R= ESET; break; case ASPEED_SDHCI_SDIO_140: - sdhci->slots[0].capareg =3D (uint64_t)(uint32_t)val; + sdhci->slots[0].capareg =3D deposit64(sdhci->slots[0].capareg, 0, = 32, val); + break; + case ASPEED_SDHCI_SDIO_144: + sdhci->slots[0].capareg =3D deposit64(sdhci->slots[0].capareg, 32,= 32, val); break; case ASPEED_SDHCI_SDIO_148: - sdhci->slots[0].maxcurr =3D (uint64_t)(uint32_t)val; + sdhci->slots[0].maxcurr =3D deposit64(sdhci->slots[0].maxcurr, + 0, 32, val); break; case ASPEED_SDHCI_SDIO_240: - sdhci->slots[1].capareg =3D (uint64_t)(uint32_t)val; + sdhci->slots[1].capareg =3D deposit64(sdhci->slots[1].capareg, + 0, 32, val); + break; + case ASPEED_SDHCI_SDIO_244: + sdhci->slots[1].capareg =3D deposit64(sdhci->slots[1].capareg, + 32, 32, val); break; case ASPEED_SDHCI_SDIO_248: - sdhci->slots[1].maxcurr =3D (uint64_t)(uint32_t)val; + sdhci->slots[1].maxcurr =3D deposit64(sdhci->slots[0].maxcurr, + 0, 32, val); break; default: if (addr < ASPEED_SDHCI_REG_SIZE) { --=20 2.47.0