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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1730715318; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KwxKjafKDnKBkadg0NOHGWyqqTRQcVmPU7A81oAJBiI=; b=cOvHolq38GU2ICFdSBPfqnHvUUKSOyOTXmc1CV45DXpEQSAzuL0j7rVdnI5wNjw7PdPvQp wpwxBCAC4fi4X1PrY2ZXMVIenaFvoKOwK6TndhMuwUBqRGOjQ5OqvWtATx7o4gCSNone9M ItJrQSAeFoq1R8Wgy2Tjl3wNzpDr8V0= X-MC-Unique: 5M6F8JWJO6ud02TEs7EC2Q-1 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Pierrick Bouvier Subject: [PULL 04/10] hw/arm/aspeed_ast27x0: Avoid hardcoded '256' in IRQ calculation Date: Mon, 4 Nov 2024 11:14:55 +0100 Message-ID: <20241104101501.2487001-5-clg@redhat.com> In-Reply-To: <20241104101501.2487001-1-clg@redhat.com> References: <20241104101501.2487001-1-clg@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Peter Maydell When calculating the index into the GIC's GPIO array for per-CPU interrupts, we have to start with the number of SPIs. The code currently hard-codes this to 'NUM_IRQS =3D 256'. However the number of SPIs is set separately and implicitly by the value of AST2700_MAX_IRQ, which is the number of SPIs plus 32 (since it is what we set the GIC num-irq property to). Define AST2700_MAX_IRQ as the total number of SPIs; this brings AST2700 into line with AST2600, which defines AST2600_MAX_IRQ as the number of SPIs not including the 32 internal interrupts. We can then use AST2700_MAX_IRQ instead of the hardcoded 256. Signed-off-by: Peter Maydell Reviewed-by: Pierrick Bouvier --- hw/arm/aspeed_ast27x0.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 5638a7a5781b..7b2464409521 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -66,7 +66,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_GPIO] =3D 0x14C0B000, }; =20 -#define AST2700_MAX_IRQ 288 +#define AST2700_MAX_IRQ 256 =20 /* Shared Peripheral Interrupt values below are offset by -32 from datashe= et */ static const int aspeed_soc_ast2700_irqmap[] =3D { @@ -403,7 +403,7 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState = *dev, Error **errp) gicdev =3D DEVICE(&a->gic); qdev_prop_set_uint32(gicdev, "revision", 3); qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); - qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ); + qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL= ); =20 redist_region_count =3D qlist_new(); qlist_append_int(redist_region_count, sc->num_cpus); @@ -417,8 +417,7 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState = *dev, Error **errp) =20 for (i =3D 0; i < sc->num_cpus; i++) { DeviceState *cpudev =3D DEVICE(&a->cpu[i]); - int NUM_IRQS =3D 256; - int intidbase =3D NUM_IRQS + i * GIC_INTERNAL; + int intidbase =3D AST2700_MAX_IRQ + i * GIC_INTERNAL; =20 const int timer_irq[] =3D { [GTIMER_PHYS] =3D ARCH_TIMER_NS_EL1_IRQ, --=20 2.47.0