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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1730715315; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kTHb1e+iHwXlenyiLDCCN2TDzp/q1TON6QHXNe/VOQY=; b=PwNcGeruN71so3+Z1Y8C2ljK8MReoBvReaFr+5qGXedSFu3B4VsteWxzt2a48VY9ppmKgm spOut8/Y6mLre8CWAgtnDH/yitLX/SXLq8neJ80Dpdq68+OTESvSMT5bQwZU7XrA7eVAHl HjsT1QAVXTzbqgSHFOlLcy4W3EcTw9I= X-MC-Unique: y64yqqUOO8OmgefVtIWuIw-1 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Pierrick Bouvier Subject: [PULL 03/10] hw/arm/aspeed_ast27x0: Use bsa.h for PPI definitions Date: Mon, 4 Nov 2024 11:14:54 +0100 Message-ID: <20241104101501.2487001-4-clg@redhat.com> In-Reply-To: <20241104101501.2487001-1-clg@redhat.com> References: <20241104101501.2487001-1-clg@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Peter Maydell Use the private peripheral interrupt definitions from bsa.h instead of defining them locally. Note that bsa.h defines these values as INTID values, which are all 16 greater than the PPI values that we were previously using. So we refactor the code to use INTID-based values to match that. This is the same thing we did in commit d40ab068c07d9 for sbsa-ref. It removes the "same constant, different values" confusion where this board code and bsa.h both define an ARCH_GIC_MAINT_IRQ, and allows us to use symbolic names for the timer interrupt IDs. Signed-off-by: Peter Maydell Reviewed-by: Pierrick Bouvier --- hw/arm/aspeed_ast27x0.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index dca660eb6be2..5638a7a5781b 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -13,6 +13,7 @@ #include "qapi/error.h" #include "hw/misc/unimp.h" #include "hw/arm/aspeed_soc.h" +#include "hw/arm/bsa.h" #include "qemu/module.h" #include "qemu/error-report.h" #include "hw/i2c/aspeed_i2c.h" @@ -416,28 +417,28 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceStat= e *dev, Error **errp) =20 for (i =3D 0; i < sc->num_cpus; i++) { DeviceState *cpudev =3D DEVICE(&a->cpu[i]); - int NUM_IRQS =3D 256, ARCH_GIC_MAINT_IRQ =3D 9, VIRTUAL_PMU_IRQ = =3D 7; - int ppibase =3D NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; + int NUM_IRQS =3D 256; + int intidbase =3D NUM_IRQS + i * GIC_INTERNAL; =20 const int timer_irq[] =3D { - [GTIMER_PHYS] =3D 14, - [GTIMER_VIRT] =3D 11, - [GTIMER_HYP] =3D 10, - [GTIMER_SEC] =3D 13, + [GTIMER_PHYS] =3D ARCH_TIMER_NS_EL1_IRQ, + [GTIMER_VIRT] =3D ARCH_TIMER_VIRT_IRQ, + [GTIMER_HYP] =3D ARCH_TIMER_NS_EL2_IRQ, + [GTIMER_SEC] =3D ARCH_TIMER_S_EL1_IRQ, }; int j; =20 for (j =3D 0; j < ARRAY_SIZE(timer_irq); j++) { qdev_connect_gpio_out(cpudev, j, - qdev_get_gpio_in(gicdev, ppibase + timer_irq[j])); + qdev_get_gpio_in(gicdev, intidbase + timer_irq[j])); } =20 qemu_irq irq =3D qdev_get_gpio_in(gicdev, - ppibase + ARCH_GIC_MAINT_IRQ); + intidbase + ARCH_GIC_MAINT_IRQ); qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, irq); qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, - qdev_get_gpio_in(gicdev, ppibase + VIRTUAL_PMU_IRQ)); + qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ)); =20 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_= IRQ)); sysbus_connect_irq(gicbusdev, i + sc->num_cpus, --=20 2.47.0