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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1730715316; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+N0l3/VFbJLlzTSBf3h/Tyd7n9TFYqg74WR1kiyhgZg=; b=ToDIdE/xRgIgLWAyueCItvegI96By4R8WUnixhjXrE0oK0nQMmrejtuEF/YbZew8dbPMyr y17jMQ2IcOaATocE2+ZdyDoqaj2PRYyCS2EZTiNBnBZ8BiENa/2v9OVe67kk5VKQj0mO1K mnx8UrI55PWUvWAR1RlyuvBNOA8JGqE= X-MC-Unique: Um-2wqQKMH6DvfkVAta5Gw-1 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Patrick Leis , Hao Wu , Andrew Jeffery , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 01/10] hw/arm: enable at24c with aspeed Date: Mon, 4 Nov 2024 11:14:52 +0100 Message-ID: <20241104101501.2487001-2-clg@redhat.com> In-Reply-To: <20241104101501.2487001-1-clg@redhat.com> References: <20241104101501.2487001-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1730715415963116600 From: Patrick Leis Enable AT24C with ASPEED in the KConfig because the boards build this device. Signed-off-by: Patrick Leis Reviewed-by: Hao Wu Reviewed-by: Andrew Jeffery Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e7fd9338d11d..1b25e73578e7 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -539,6 +539,7 @@ config ASPEED_SOC select PMBUS select MAX31785 select FSI_APB2OPB_ASPEED + select AT24C =20 config MPS2 bool --=20 2.47.0 From nobody Sat Nov 23 20:42:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1730715426; cv=none; d=zohomail.com; s=zohoarc; b=IBtLd+lrqliUe80Duo76GNamXyh0DgTvQ6raXtCkNupimxbk61gmM3780fdmr1oZ+6ACBC2OlytUtwcqKwYk2rmETWnQ6K70TDUOWE9eIaMNhFpguF6+ms1EVEzjNDCzyPmAFVZ5Sfjx/kMT2f3Fe2CLYJzZ0YgD4NLFg6ggFcM= ARC-Message-Signature: i=1; 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Mon, 4 Nov 2024 10:15:11 +0000 (UTC) Received: from corto.redhat.com (unknown [10.39.192.67]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id EF71C1955F40; Mon, 4 Nov 2024 10:15:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1730715315; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xzjU1g3JiGJotP6otX8pU85ptag0kOQoUbS3ylFujAw=; b=dFeS3xqa8hqF9VNSaQkunP4HV1UJjViQSr8TrqW89YKFw0x28+xxdOxcCti4XwWgVibVgl 4CR2uJ+mc96Vd6mEsw1uxxF98TDUe1ilpaWIlyWhlyjXmTKFitPf536fwM6sILwLAPLTnM MCrSFTMd1Ajqgz0/CGUfOFJ9MgJHQy4= X-MC-Unique: 89-aVbhNOiedmt5namBC3Q-1 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jan Luebbe , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Guenter Roeck , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 02/10] hw/sd/sdcard: Fix calculation of size when using eMMC boot partitions Date: Mon, 4 Nov 2024 11:14:53 +0100 Message-ID: <20241104101501.2487001-3-clg@redhat.com> In-Reply-To: <20241104101501.2487001-1-clg@redhat.com> References: <20241104101501.2487001-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1730715427974116600 From: Jan Luebbe The sd_bootpart_offset() function calculates the *runtime* offset which changes as the guest switches between accessing the main user data area and the boot partitions by writing to the EXT_CSD_PART_CONFIG_ACC_MASK bits, so it shouldn't be used to calculate the main user data area size. Instead, subtract the boot_part_size directly (twice, as there are two identical boot partitions defined by the eMMC spec). Suggested-by: C=C3=A9dric Le Goater Signed-off-by: Jan Luebbe Fixes: c8cb19876d3e ("hw/sd/sdcard: Support boot area in emmc image") Tested-by: Guenter Roeck Reviewed-by: C=C3=A9dric Le Goater --- hw/sd/sd.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index b2e2d58e013e..f9bd03f3fd9e 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -834,7 +834,9 @@ static void sd_reset(DeviceState *dev) sect =3D 0; } size =3D sect << HWBLOCK_SHIFT; - size -=3D sd_bootpart_offset(sd); + if (sd_is_emmc(sd)) { + size -=3D sd->boot_part_size * 2; + } =20 sect =3D sd_addr_to_wpnum(size) + 1; =20 --=20 2.47.0 From nobody Sat Nov 23 20:42:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1730715452; 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Mon, 4 Nov 2024 10:15:13 +0000 (UTC) Received: from corto.redhat.com (unknown [10.39.192.67]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id B66941956052; Mon, 4 Nov 2024 10:15:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1730715315; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kTHb1e+iHwXlenyiLDCCN2TDzp/q1TON6QHXNe/VOQY=; b=PwNcGeruN71so3+Z1Y8C2ljK8MReoBvReaFr+5qGXedSFu3B4VsteWxzt2a48VY9ppmKgm spOut8/Y6mLre8CWAgtnDH/yitLX/SXLq8neJ80Dpdq68+OTESvSMT5bQwZU7XrA7eVAHl HjsT1QAVXTzbqgSHFOlLcy4W3EcTw9I= X-MC-Unique: y64yqqUOO8OmgefVtIWuIw-1 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Pierrick Bouvier Subject: [PULL 03/10] hw/arm/aspeed_ast27x0: Use bsa.h for PPI definitions Date: Mon, 4 Nov 2024 11:14:54 +0100 Message-ID: <20241104101501.2487001-4-clg@redhat.com> In-Reply-To: <20241104101501.2487001-1-clg@redhat.com> References: <20241104101501.2487001-1-clg@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Peter Maydell Use the private peripheral interrupt definitions from bsa.h instead of defining them locally. Note that bsa.h defines these values as INTID values, which are all 16 greater than the PPI values that we were previously using. So we refactor the code to use INTID-based values to match that. This is the same thing we did in commit d40ab068c07d9 for sbsa-ref. It removes the "same constant, different values" confusion where this board code and bsa.h both define an ARCH_GIC_MAINT_IRQ, and allows us to use symbolic names for the timer interrupt IDs. Signed-off-by: Peter Maydell Reviewed-by: Pierrick Bouvier --- hw/arm/aspeed_ast27x0.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index dca660eb6be2..5638a7a5781b 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -13,6 +13,7 @@ #include "qapi/error.h" #include "hw/misc/unimp.h" #include "hw/arm/aspeed_soc.h" +#include "hw/arm/bsa.h" #include "qemu/module.h" #include "qemu/error-report.h" #include "hw/i2c/aspeed_i2c.h" @@ -416,28 +417,28 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceStat= e *dev, Error **errp) =20 for (i =3D 0; i < sc->num_cpus; i++) { DeviceState *cpudev =3D DEVICE(&a->cpu[i]); - int NUM_IRQS =3D 256, ARCH_GIC_MAINT_IRQ =3D 9, VIRTUAL_PMU_IRQ = =3D 7; - int ppibase =3D NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; + int NUM_IRQS =3D 256; + int intidbase =3D NUM_IRQS + i * GIC_INTERNAL; =20 const int timer_irq[] =3D { - [GTIMER_PHYS] =3D 14, - [GTIMER_VIRT] =3D 11, - [GTIMER_HYP] =3D 10, - [GTIMER_SEC] =3D 13, + [GTIMER_PHYS] =3D ARCH_TIMER_NS_EL1_IRQ, + [GTIMER_VIRT] =3D ARCH_TIMER_VIRT_IRQ, + [GTIMER_HYP] =3D ARCH_TIMER_NS_EL2_IRQ, + [GTIMER_SEC] =3D ARCH_TIMER_S_EL1_IRQ, }; int j; =20 for (j =3D 0; j < ARRAY_SIZE(timer_irq); j++) { qdev_connect_gpio_out(cpudev, j, - qdev_get_gpio_in(gicdev, ppibase + timer_irq[j])); + qdev_get_gpio_in(gicdev, intidbase + timer_irq[j])); } =20 qemu_irq irq =3D qdev_get_gpio_in(gicdev, - ppibase + ARCH_GIC_MAINT_IRQ); + intidbase + ARCH_GIC_MAINT_IRQ); qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, irq); qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, - qdev_get_gpio_in(gicdev, ppibase + VIRTUAL_PMU_IRQ)); + qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ)); =20 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_= IRQ)); sysbus_connect_irq(gicbusdev, i + sc->num_cpus, --=20 2.47.0 From nobody Sat Nov 23 20:42:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; 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Mon, 04 Nov 2024 05:15:16 -0500 Received: from mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.17]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id ED5F41944D3C; Mon, 4 Nov 2024 10:15:14 +0000 (UTC) Received: from corto.redhat.com (unknown [10.39.192.67]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 8F59F1956052; Mon, 4 Nov 2024 10:15:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1730715318; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KwxKjafKDnKBkadg0NOHGWyqqTRQcVmPU7A81oAJBiI=; b=cOvHolq38GU2ICFdSBPfqnHvUUKSOyOTXmc1CV45DXpEQSAzuL0j7rVdnI5wNjw7PdPvQp wpwxBCAC4fi4X1PrY2ZXMVIenaFvoKOwK6TndhMuwUBqRGOjQ5OqvWtATx7o4gCSNone9M ItJrQSAeFoq1R8Wgy2Tjl3wNzpDr8V0= X-MC-Unique: 5M6F8JWJO6ud02TEs7EC2Q-1 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Pierrick Bouvier Subject: [PULL 04/10] hw/arm/aspeed_ast27x0: Avoid hardcoded '256' in IRQ calculation Date: Mon, 4 Nov 2024 11:14:55 +0100 Message-ID: <20241104101501.2487001-5-clg@redhat.com> In-Reply-To: <20241104101501.2487001-1-clg@redhat.com> References: <20241104101501.2487001-1-clg@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1730715385668116600 Content-Type: text/plain; charset="utf-8" From: Peter Maydell When calculating the index into the GIC's GPIO array for per-CPU interrupts, we have to start with the number of SPIs. The code currently hard-codes this to 'NUM_IRQS =3D 256'. However the number of SPIs is set separately and implicitly by the value of AST2700_MAX_IRQ, which is the number of SPIs plus 32 (since it is what we set the GIC num-irq property to). Define AST2700_MAX_IRQ as the total number of SPIs; this brings AST2700 into line with AST2600, which defines AST2600_MAX_IRQ as the number of SPIs not including the 32 internal interrupts. We can then use AST2700_MAX_IRQ instead of the hardcoded 256. Signed-off-by: Peter Maydell Reviewed-by: Pierrick Bouvier --- hw/arm/aspeed_ast27x0.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 5638a7a5781b..7b2464409521 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -66,7 +66,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_GPIO] =3D 0x14C0B000, }; =20 -#define AST2700_MAX_IRQ 288 +#define AST2700_MAX_IRQ 256 =20 /* Shared Peripheral Interrupt values below are offset by -32 from datashe= et */ static const int aspeed_soc_ast2700_irqmap[] =3D { @@ -403,7 +403,7 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState = *dev, Error **errp) gicdev =3D DEVICE(&a->gic); qdev_prop_set_uint32(gicdev, "revision", 3); qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); - qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ); + qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL= ); =20 redist_region_count =3D qlist_new(); qlist_append_int(redist_region_count, sc->num_cpus); @@ -417,8 +417,7 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState = *dev, Error **errp) =20 for (i =3D 0; i < sc->num_cpus; i++) { DeviceState *cpudev =3D DEVICE(&a->cpu[i]); - int NUM_IRQS =3D 256; - int intidbase =3D NUM_IRQS + i * GIC_INTERNAL; + int intidbase =3D AST2700_MAX_IRQ + i * GIC_INTERNAL; =20 const int timer_irq[] =3D { [GTIMER_PHYS] =3D ARCH_TIMER_NS_EL1_IRQ, --=20 2.47.0 From nobody Sat Nov 23 20:42:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1730715378; cv=none; d=zohomail.com; s=zohoarc; b=HkU6C+k9jzQPjKmETswfmTX3LA22rkLA2eWpCP4NV826hDEpz14brChPhJ0AOkoWrOqFBps9k4z4bbQ5Ub44HbPFGw7+sX7Mnz+wAbK08xSkqYfvaODB7sPDNlQ0jWCa4MIgt7gxI3iOmcLxK8B8JgVO1iVM7KnIivtJUk5abIo= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1730715380063116600 From: Jamin Lin The RTC controller between AST2600 and AST2700 are identical. Add RTC model= for AST2700 RTC support. The RTC controller registers base address is start at 0x12C0_F000 and its alarm interrupt is connected to GICINT13. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast27x0.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 7b2464409521..63d1fcb086d7 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -64,6 +64,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_ADC] =3D 0x14C00000, [ASPEED_DEV_I2C] =3D 0x14C0F000, [ASPEED_DEV_GPIO] =3D 0x14C0B000, + [ASPEED_DEV_RTC] =3D 0x12C0F000, }; =20 #define AST2700_MAX_IRQ 256 @@ -377,6 +378,8 @@ static void aspeed_soc_ast2700_init(Object *obj) =20 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); object_initialize_child(obj, "gpio", &s->gpio, typename); + + object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); } =20 /* @@ -670,6 +673,14 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); =20 + /* RTC */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { + return; + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_R= TC]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, + aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); + create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000); create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000); create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000); --=20 2.47.0 From nobody Sat Nov 23 20:42:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1730715415; cv=none; d=zohomail.com; s=zohoarc; b=S65SFpDPUf2eNiSqvIJ9smvp2RaxNV1K2FkCIRNOZ+PJulJQPeccPN6T+7h9shtLnXI63CIBux4IolADel11NWrES+LJdpoMcnbcxxug+4cLuJTTlN5f3FNRVTOqJBQrvVFwo/P+qUp4RRfQUqwaYpYZiZqDNyp8+VDApoHvCK4= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1730715417981116600 From: Jamin Lin Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/timer/aspeed_timer.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index b1f860ecfb80..5af268ea9ebc 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -276,7 +276,8 @@ static void aspeed_timer_set_value(AspeedTimerCtrlState= *s, int timer, int reg, old_reload =3D t->reload; t->reload =3D calculate_min_ticks(t, value); =20 - /* If the reload value was not previously set, or zero, and + /* + * If the reload value was not previously set, or zero, and * the current value is valid, try to start the timer if it is * enabled. */ @@ -312,7 +313,8 @@ static void aspeed_timer_set_value(AspeedTimerCtrlState= *s, int timer, int reg, } } =20 -/* Control register operations are broken out into helpers that can be +/* + * Control register operations are broken out into helpers that can be * explicitly called on aspeed_timer_reset(), but also from * aspeed_timer_ctrl_op(). */ @@ -396,7 +398,8 @@ static void aspeed_timer_set_ctrl(AspeedTimerCtrlState = *s, uint32_t reg) AspeedTimer *t; const uint8_t enable_mask =3D BIT(op_enable); =20 - /* Handle a dependency between the 'enable' and remaining three + /* + * Handle a dependency between the 'enable' and remaining three * configuration bits - i.e. if more than one bit in the control set h= as * changed, including the 'enable' bit, then we want either disable the * timer and perform configuration, or perform configuration and then @@ -582,7 +585,6 @@ static void aspeed_2600_timer_write(AspeedTimerCtrlStat= e *s, hwaddr offset, case 0x3C: aspeed_timer_set_ctrl(s, s->ctrl & ~tv); break; - case 0x38: default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\= n", @@ -623,7 +625,8 @@ static void aspeed_timer_reset(DeviceState *dev) =20 for (i =3D 0; i < ASPEED_TIMER_NR_TIMERS; i++) { AspeedTimer *t =3D &s->timers[i]; - /* Explicitly call helpers to avoid any conditional behaviour thro= ugh + /* + * Explicitly call helpers to avoid any conditional behaviour thro= ugh * aspeed_timer_set_ctrl(). */ aspeed_timer_ctrl_enable(t, false); --=20 2.47.0 From nobody Sat Nov 23 20:42:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1730715378; cv=none; d=zohomail.com; s=zohoarc; b=h8tAhtwtkHuReNnmlmnZAmx1nVxYT7xcZB0XtYvuPLbZ1bjR8TQC3i9QCVDrxuBPRIkvi+2wsmvcJ7J/zvo0uwM38hIzBdNquplXa4YvuP6ltQaUeIylUoDDnIwHZGwCjbZWSWXyfHUD7fIbBJIukDYMP4gV/huHadz5i6Ep/E4= ARC-Message-Signature: i=1; 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Mon, 4 Nov 2024 10:15:23 +0000 (UTC) Received: from corto.redhat.com (unknown [10.39.192.67]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id E75E21955F40; Mon, 4 Nov 2024 10:15:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1730715326; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=e6gaduAfI+wCpuhXs1Wv9w9ku29RoqogCLvniLhjI80=; b=E102tEJdG4DYdkwfECJqfQro5bHk+58hS65mnvFX7FLf0V63yiMrkGs3YpOgq2z3GNQ/gd bSx4Rq1DlqfJQvOpyGlVQlVH+kuhT5FrqCBXKs0beZJ4Ai1vkdTlaQo9m9e/sz3KhSc3iv Pc1SgSj6eg8lpcciH1oZZCkIscPbjmc= X-MC-Unique: -CQhXOCSOriD7gi-H_GCQg-1 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 07/10] hw/timer/aspeed: Fix interrupt status does not be cleared for AST2600 Date: Mon, 4 Nov 2024 11:14:58 +0100 Message-ID: <20241104101501.2487001-8-clg@redhat.com> In-Reply-To: <20241104101501.2487001-1-clg@redhat.com> References: <20241104101501.2487001-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1730715380029116600 From: Jamin Lin According to the datasheet of AST2600 description, interrupt status set by = HW and clear to "0" by software writing "1" on the specific bit. Therefore, if firmware set the specific bit "1" in the interrupt status register(0x34), the specific bit of "s->irq_sts" should be cleared 0. Signed-off-by: Jamin Lin Fixes: fadefada4d07 ("aspeed/timer: Add support for IRQ status register on = the AST2600") Reviewed-by: Andrew Jeffery Reviewed-by: C=C3=A9dric Le Goater --- hw/timer/aspeed_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 5af268ea9ebc..149f7cc5a6aa 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -580,7 +580,7 @@ static void aspeed_2600_timer_write(AspeedTimerCtrlStat= e *s, hwaddr offset, =20 switch (offset) { case 0x34: - s->irq_sts &=3D tv; + s->irq_sts &=3D ~tv; break; case 0x3C: aspeed_timer_set_ctrl(s, s->ctrl & ~tv); --=20 2.47.0 From nobody Sat Nov 23 20:42:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; 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bh=BZdvH/GfNWMkDbJPcCePcYhrbzcwgt3JfPMq8q8/Fw4=; b=VrNlEtaO5asGWdHTMKRJExEUYsqutRvlyfxCBTO7Q/KaTyGmkzqDZC1qko7LiSh/WYxQE5 m7M5+zsENQoN7PnLLmBPBx6a6Th2G+zm1kQqWB4BJ+ISoiEzderj2jeLJSjN7wD+tyC23a Y3BhF4/tfsjuaeDcl/eWW1bft4r6w4o= X-MC-Unique: YpOLog55PROVv3s6QsUvaQ-1 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 08/10] hw/sd/aspeed_sdhci: Introduce Capabilities Register 2 for SD slot 0 and 1 Date: Mon, 4 Nov 2024 11:14:59 +0100 Message-ID: <20241104101501.2487001-9-clg@redhat.com> In-Reply-To: <20241104101501.2487001-1-clg@redhat.com> References: <20241104101501.2487001-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1730715439890116600 From: Jamin Lin The size of SDHCI capabilities register is 64bits, so introduces new Capabilities Register 2 for SD slot 0 (0x144) and SD slot1 (0x244). Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater [ clg: Fixed code alignment ] Signed-off-by: C=C3=A9dric Le Goater --- hw/sd/aspeed_sdhci.c | 40 +++++++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 11 deletions(-) diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c index 427e5336a8fb..98d5460905df 100644 --- a/hw/sd/aspeed_sdhci.c +++ b/hw/sd/aspeed_sdhci.c @@ -24,8 +24,10 @@ #define ASPEED_SDHCI_DEBOUNCE_RESET 0x00000005 #define ASPEED_SDHCI_BUS 0x08 #define ASPEED_SDHCI_SDIO_140 0x10 +#define ASPEED_SDHCI_SDIO_144 0x14 #define ASPEED_SDHCI_SDIO_148 0x18 #define ASPEED_SDHCI_SDIO_240 0x20 +#define ASPEED_SDHCI_SDIO_244 0x24 #define ASPEED_SDHCI_SDIO_248 0x28 #define ASPEED_SDHCI_WP_POL 0xec #define ASPEED_SDHCI_CARD_DET 0xf0 @@ -35,21 +37,27 @@ =20 static uint64_t aspeed_sdhci_read(void *opaque, hwaddr addr, unsigned int = size) { - uint32_t val =3D 0; + uint64_t val =3D 0; AspeedSDHCIState *sdhci =3D opaque; =20 switch (addr) { case ASPEED_SDHCI_SDIO_140: - val =3D (uint32_t)sdhci->slots[0].capareg; + val =3D extract64(sdhci->slots[0].capareg, 0, 32); + break; + case ASPEED_SDHCI_SDIO_144: + val =3D extract64(sdhci->slots[0].capareg, 32, 32); break; case ASPEED_SDHCI_SDIO_148: - val =3D (uint32_t)sdhci->slots[0].maxcurr; + val =3D extract64(sdhci->slots[0].maxcurr, 0, 32); break; case ASPEED_SDHCI_SDIO_240: - val =3D (uint32_t)sdhci->slots[1].capareg; + val =3D extract64(sdhci->slots[1].capareg, 0, 32); + break; + case ASPEED_SDHCI_SDIO_244: + val =3D extract64(sdhci->slots[1].capareg, 32, 32); break; case ASPEED_SDHCI_SDIO_248: - val =3D (uint32_t)sdhci->slots[1].maxcurr; + val =3D extract64(sdhci->slots[1].maxcurr, 0, 32); break; default: if (addr < ASPEED_SDHCI_REG_SIZE) { @@ -61,9 +69,9 @@ static uint64_t aspeed_sdhci_read(void *opaque, hwaddr ad= dr, unsigned int size) } } =20 - trace_aspeed_sdhci_read(addr, size, (uint64_t) val); + trace_aspeed_sdhci_read(addr, size, val); =20 - return (uint64_t)val; + return val; } =20 static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val, @@ -79,16 +87,26 @@ static void aspeed_sdhci_write(void *opaque, hwaddr add= r, uint64_t val, sdhci->regs[TO_REG(addr)] =3D (uint32_t)val & ~ASPEED_SDHCI_INFO_R= ESET; break; case ASPEED_SDHCI_SDIO_140: - sdhci->slots[0].capareg =3D (uint64_t)(uint32_t)val; + sdhci->slots[0].capareg =3D deposit64(sdhci->slots[0].capareg, 0, = 32, val); + break; + case ASPEED_SDHCI_SDIO_144: + sdhci->slots[0].capareg =3D deposit64(sdhci->slots[0].capareg, 32,= 32, val); break; case ASPEED_SDHCI_SDIO_148: - sdhci->slots[0].maxcurr =3D (uint64_t)(uint32_t)val; + sdhci->slots[0].maxcurr =3D deposit64(sdhci->slots[0].maxcurr, + 0, 32, val); break; case ASPEED_SDHCI_SDIO_240: - sdhci->slots[1].capareg =3D (uint64_t)(uint32_t)val; + sdhci->slots[1].capareg =3D deposit64(sdhci->slots[1].capareg, + 0, 32, val); + break; + case ASPEED_SDHCI_SDIO_244: + sdhci->slots[1].capareg =3D deposit64(sdhci->slots[1].capareg, + 32, 32, val); break; case ASPEED_SDHCI_SDIO_248: - sdhci->slots[1].maxcurr =3D (uint64_t)(uint32_t)val; + sdhci->slots[1].maxcurr =3D deposit64(sdhci->slots[0].maxcurr, + 0, 32, val); break; default: if (addr < ASPEED_SDHCI_REG_SIZE) { --=20 2.47.0 From nobody Sat Nov 23 20:42:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1730715331; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wURCA/J3t3nlSwY6omLtbIcXXCMyGEwLA4Zktk+w0jw=; b=gl71ulpp+YtmDgYluM6Q3latcusfk/Q/A1e4WS+uXdCpPWW9MeKZq9Ffs70fg/95YLZcHH 6aFdAkdJNgx/KbuD/W/7Dwq15Dmpek53WyXHKoWUTBK1AuQ8yyZMjRS/7F3x+gMDTrCYGX tgY+89sQeZxhDN6h+kB22rdD3FmGs0o= X-MC-Unique: FTDcEMctNi2gYfXBtJvkLg-1 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 09/10] aspeed: Support create flash devices via command line for AST1030 Date: Mon, 4 Nov 2024 11:15:00 +0100 Message-ID: <20241104101501.2487001-10-clg@redhat.com> In-Reply-To: <20241104101501.2487001-1-clg@redhat.com> References: <20241104101501.2487001-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1730715448213116600 From: Jamin Lin Add a "if-statement" in aspeed_minibmc_machine_init function. If users add "-nodefaults" in command line, the flash devices should be created by users setting. Otherwise, the flash devices are created at machine init. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index b4b1ce9efb2b..e447923536b4 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1594,18 +1594,20 @@ static void aspeed_minibmc_machine_init(MachineStat= e *machine) connect_serial_hds_to_uarts(bmc); qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); =20 - aspeed_board_init_flashes(&bmc->soc->fmc, - bmc->fmc_model ? bmc->fmc_model : amc->fmc_m= odel, - amc->num_cs, - 0); + if (defaults_enabled()) { + aspeed_board_init_flashes(&bmc->soc->fmc, + bmc->fmc_model ? bmc->fmc_model : amc->fmc_mod= el, + amc->num_cs, + 0); =20 - aspeed_board_init_flashes(&bmc->soc->spi[0], - bmc->spi_model ? bmc->spi_model : amc->spi_m= odel, - amc->num_cs, amc->num_cs); + aspeed_board_init_flashes(&bmc->soc->spi[0], + bmc->spi_model ? bmc->spi_model : amc->spi_mod= el, + amc->num_cs, amc->num_cs); =20 - aspeed_board_init_flashes(&bmc->soc->spi[1], - bmc->spi_model ? bmc->spi_model : amc->spi_m= odel, - amc->num_cs, (amc->num_cs * 2)); + aspeed_board_init_flashes(&bmc->soc->spi[1], + bmc->spi_model ? bmc->spi_model : amc->spi_mod= el, + amc->num_cs, (amc->num_cs * 2)); + } =20 if (amc->i2c_init) { amc->i2c_init(bmc); --=20 2.47.0 From nobody Sat Nov 23 20:42:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1730715448; cv=none; d=zohomail.com; s=zohoarc; b=G/EoDZg/1bTKzYM6wqGeyFeIZjf3lmqfIRdZQC670XZaiNlYH26BGWQKaP6LwsHguGV0s1gD7jae5VcQUw8b7eKcbm2By9xoRlk3tShodttgRhhd0/4eDyxgjPG4ZOp9EqWCZTuqbIySpW6XvMnwYBU8EHkAvoH46QVrOQT7eJY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730715448; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Mon, 4 Nov 2024 10:15:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1730715334; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tVjafkZnyxLi3ipSWKwXdxnsAegwe+glEiTN1gXul0Y=; b=Qe0Q+X6YV/VWRsRQRRb0EZuZor9u3yy5tP8jugwVyiLImH19UA5Q/RkluyWC4Mk4y2/1d5 Jmeqj3GQDXhj6JTy/uBObiy/YujyAnPaBJ+eMVzAmKgiMjs/qa3Mv1S2NHYZ1dRDtLxhSr CHzURy5FPnUqj1hJs04ZLu+eVbZLlSA= X-MC-Unique: MzM_2Z0OMz6-inl4uFfUgQ-1 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Jan Luebbe , Guenter Roeck Subject: [PULL 10/10] aspeed: Don't set always boot properties of the emmc device Date: Mon, 4 Nov 2024 11:15:01 +0100 Message-ID: <20241104101501.2487001-11-clg@redhat.com> In-Reply-To: <20241104101501.2487001-1-clg@redhat.com> References: <20241104101501.2487001-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1730715450008116600 Commit e554e45b4478 ("aspeed: Tune eMMC device properties to reflect HW strapping") added support to boot from an eMMC device by setting the boot properties of the eMMC device. This change made the assumption that the device always has boot areas. However, if the machine boots from the flash device (or -kernel) and uses an eMMC device without boot areas, support would be broken. This impacts the ast2600-evb machine which can choose to boot from flash or eMMC using the "boot-emmc" machine option. To provide some flexibility for Aspeed machine users to use different flavors of eMMC devices (with or without boot areas), do not set the eMMC device boot properties when the machine is not configured to boot from eMMC. However, this approach makes another assumption about eMMC devices, namely that eMMC devices from which the machine does not boot do not have boot areas. A preferable alternative would be to add support for user creatable eMMC devices and define the device boot properties on the QEMU command line : -blockdev node-name=3Demmc0,driver=3Dfile,filename=3Dmmc-ast2600-evb.raw \ -device emmc,bus=3Dsdhci-bus.2,drive=3Demmc0,boot-partition-size=3D104857= 6,boot-config=3D8 This is a global change requiring more thinking. Nevertheless, in the case of the ast2600-evb machine booting from an eMMC device and when default devices are created, the proposed change still makes sense since the device is required to have boot areas. Cc: Jan Luebbe Fixes: e554e45b4478 ("aspeed: Tune eMMC device properties to reflect HW strapping") Signed-off-by: C=C3=A9dric Le Goater Tested-by: Guenter Roeck Reviewed-by: Jan Luebbe --- hw/arm/aspeed.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index e447923536b4..6ca145362cbd 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -338,10 +338,20 @@ static void sdhci_attach_drive(SDHCIState *sdhci, Dri= veInfo *dinfo, bool emmc, return; } card =3D qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD); - if (emmc) { + + /* + * Force the boot properties of the eMMC device only when the + * machine is strapped to boot from eMMC. Without these + * settings, the machine would not boot. + * + * This also allows the machine to use an eMMC device without + * boot areas when booting from the flash device (or -kernel) + * Ideally, the device and its properties should be defined on + * the command line. + */ + if (emmc && boot_emmc) { qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB); - qdev_prop_set_uint8(card, "boot-config", - boot_emmc ? 0x1 << 3 : 0x0); + qdev_prop_set_uint8(card, "boot-config", 0x1 << 3); } qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), &error_fatal); --=20 2.47.0