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Mon, 4 Nov 2024 09:41:54 GMT Received: from localhost.localdomain (ca-dev80.us.oracle.com [10.211.9.80]) by iadpaimrmta03.imrmtpd1.prodappiadaev1.oraclevcn.com (PPS) with ESMTP id 42nahbt06k-2; Mon, 04 Nov 2024 09:41:53 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2023-11-20; bh=8dj9+ Fj2Y7+fcJzsYZdCfnhnZ64eJxfakPqpai/l9Oc=; b=UsR1EPUSgMA/8T3Uj4kdO IOMuRDOvkNtmec6hplYuqak/t05nN03z2SzN7ywRj462Mmg63oZ3g7VWZDBwtG3E fFNgIyI0SNSM5X5RjlrWki5kWOLZEDfMIsaDlityqtvuJoamNgBYvmJSvv6Nqkew 6AEiuTWyABosn7lJ+mXuhOKiEXLgK+2W+hx5Cb6ePcnN8Jtm4CLuQxm+6Y1lihu8 72BnNJe1ctP1YUXea5AmSXlgRUv2sweKIARO6AjWrIIAmJmSVLrp9jNS68HKD4cR EyzZ5AsU7KMp1SkB+R9VLNIn0tIGgVH2wVndFLkYFyBeWsBasnS9XmbwKFMVWpjz A== From: Dongli Zhang To: qemu-devel@nongnu.org, kvm@vger.kernel.org Cc: pbonzini@redhat.com, mtosatti@redhat.com, sandipan.das@amd.com, babu.moger@amd.com, zhao1.liu@intel.com, likexu@tencent.com, like.xu.linux@gmail.com, zhenyuw@linux.intel.com, groug@kaod.org, lyan@digitalocean.com, khorenko@virtuozzo.com, alexander.ivanov@virtuozzo.com, den@virtuozzo.com, joe.jin@oracle.com, davydov-max@yandex-team.ru Subject: [PATCH 1/7] target/i386: disable PerfMonV2 when PERFCORE unavailable Date: Mon, 4 Nov 2024 01:40:16 -0800 Message-ID: <20241104094119.4131-2-dongli.zhang@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20241104094119.4131-1-dongli.zhang@oracle.com> References: <20241104094119.4131-1-dongli.zhang@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-11-04_07,2024-11-01_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 phishscore=0 mlxlogscore=999 mlxscore=0 suspectscore=0 bulkscore=0 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2409260000 definitions=main-2411040085 X-Proofpoint-ORIG-GUID: Q3sRATBTcJgcGAcqpnTcqUfqFtcCcV9- X-Proofpoint-GUID: Q3sRATBTcJgcGAcqpnTcqUfqFtcCcV9- Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" When the PERFCORE is disabled with "-cpu host,-perfctr-core", it is reflected in in guest dmesg. [ 0.285136] Performance Events: AMD PMU driver. However, the guest cpuid indicates the PerfMonV2 is still available. CPU: Extended Performance Monitoring and Debugging (0x80000022): AMD performance monitoring V2 =3D true AMD LBR V2 =3D false AMD LBR stack & PMC freezing =3D false number of core perf ctrs =3D 0x6 (6) number of LBR stack entries =3D 0x0 (0) number of avail Northbridge perf ctrs =3D 0x0 (0) number of available UMC PMCs =3D 0x0 (0) active UMCs bitmask =3D 0x0 Disable PerfMonV2 in cpuid when PERFCORE is disabled. Fixes: 209b0ac12074 ("target/i386: Add PerfMonV2 feature bit") Signed-off-by: Dongli Zhang --- target/i386/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3baa95481f..4490a7a8d6 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7103,6 +7103,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *eax =3D *ebx =3D *ecx =3D *edx =3D 0; /* AMD Extended Performance Monitoring and Debug */ if (kvm_enabled() && cpu->enable_pmu && + (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_PERFCORE) && (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFM= ON_V2)) { *eax |=3D CPUID_8000_0022_EAX_PERFMON_V2; *ebx |=3D kvm_arch_get_supported_cpuid(cs->kvm_state, index, c= ount, --=20 2.39.3 From nobody Sat Nov 23 20:53:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2023-11-20; bh=bfLnj bxcSPm6lnfdVUJ780ERZUAYKYTQqq6FUng196c=; b=dxuYMhMH5AjRDPqLOREeT hmt78JhXZJXgnn5T/Ymq+vGMJeCfOKIR/y09h4S0u4U8SHkOiT0H1dzITAilUavs gPIQJETp55L1fL7KeQ0u2StgztyWY7edfvnf2c7HMKENiO+e11f/bBxAIs86+49H dlHzVqSvUmtXZIfiY84hcdk0iPRS4vOFttlCF2HEUFvK1EclKCIiNZubBZ5rBT6w 4Atn1aDd4qIjGIlEm/lTaSpTyBIagXXQlz/Own3MNXL2FIG/TEf9EcTmlQLpXQS1 Hg+KB75aly7BVbbB41EL0D5QRK3qRQEYolBhVfx2oaM2rRAEL5bRmXf53uah5kX3 g== From: Dongli Zhang To: qemu-devel@nongnu.org, kvm@vger.kernel.org Cc: pbonzini@redhat.com, mtosatti@redhat.com, sandipan.das@amd.com, babu.moger@amd.com, zhao1.liu@intel.com, likexu@tencent.com, like.xu.linux@gmail.com, zhenyuw@linux.intel.com, groug@kaod.org, lyan@digitalocean.com, khorenko@virtuozzo.com, alexander.ivanov@virtuozzo.com, den@virtuozzo.com, joe.jin@oracle.com, davydov-max@yandex-team.ru Subject: [PATCH 2/7] target/i386/kvm: introduce 'pmu-cap-disabled' to set KVM_PMU_CAP_DISABLE Date: Mon, 4 Nov 2024 01:40:17 -0800 Message-ID: <20241104094119.4131-3-dongli.zhang@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20241104094119.4131-1-dongli.zhang@oracle.com> References: <20241104094119.4131-1-dongli.zhang@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-11-04_07,2024-11-01_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 phishscore=0 mlxlogscore=999 mlxscore=0 suspectscore=0 bulkscore=0 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2409260000 definitions=main-2411040085 X-Proofpoint-GUID: akal7AZncT7cVfEwlijF__SDIscOosvs X-Proofpoint-ORIG-GUID: akal7AZncT7cVfEwlijF__SDIscOosvs Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" The AMD PMU virtualization is not disabled when configuring "-cpu host,-pmu" in the QEMU command line on an AMD server. Neither "-cpu host,-pmu" nor "-cpu EPYC" effectively disables AMD PMU virtualization in such an environment. As a result, VM logs typically show: [ 0.510611] Performance Events: Fam17h+ core perfctr, AMD PMU driver. whereas the expected logs should be: [ 0.596381] Performance Events: PMU not available due to virtualization,= using software events only. [ 0.600972] NMI watchdog: Perf NMI watchdog permanently disabled This discrepancy occurs because AMD PMU does not use CPUID to determine whether PMU virtualization is supported. To address this, we introduce a new property, 'pmu-cap-disabled', for KVM acceleration. This property sets KVM_PMU_CAP_DISABLE if KVM_CAP_PMU_CAPABILITY is supported. Note that this feature currently supports only x86 hosts, as KVM_CAP_PMU_CAPABILITY is used exclusively for x86 systems. Signed-off-by: Dongli Zhang --- Another previous solution to re-use '-cpu host,-pmu': https://lore.kernel.org/all/20221119122901.2469-1-dongli.zhang@oracle.com/ accel/kvm/kvm-all.c | 1 + include/sysemu/kvm_int.h | 1 + qemu-options.hx | 9 ++++++- target/i386/cpu.c | 2 +- target/i386/kvm/kvm.c | 52 ++++++++++++++++++++++++++++++++++++++ target/i386/kvm/kvm_i386.h | 2 ++ 6 files changed, 65 insertions(+), 2 deletions(-) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 801cff16a5..8b5ba45cf7 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -3933,6 +3933,7 @@ static void kvm_accel_instance_init(Object *obj) s->xen_evtchn_max_pirq =3D 256; s->device =3D NULL; s->msr_energy.enable =3D false; + s->pmu_cap_disabled =3D false; } =20 /** diff --git a/include/sysemu/kvm_int.h b/include/sysemu/kvm_int.h index a1e72763da..cdee1a481c 100644 --- a/include/sysemu/kvm_int.h +++ b/include/sysemu/kvm_int.h @@ -166,6 +166,7 @@ struct KVMState uint16_t xen_gnttab_max_frames; uint16_t xen_evtchn_max_pirq; char *device; + bool pmu_cap_disabled; }; =20 void kvm_memory_listener_register(KVMState *s, KVMMemoryListener *kml, diff --git a/qemu-options.hx b/qemu-options.hx index dacc9790a4..9684424835 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -191,7 +191,8 @@ DEF("accel", HAS_ARG, QEMU_OPTION_accel, " eager-split-size=3Dn (KVM Eager Page Split chunk size= , default 0, disabled. ARM only)\n" " notify-vmexit=3Drun|internal-error|disable,notify-win= dow=3Dn (enable notify VM exit and set notify window, x86 only)\n" " thread=3Dsingle|multi (enable multi-threaded TCG)\n" - " device=3Dpath (KVM device path, default /dev/kvm)\n",= QEMU_ARCH_ALL) + " device=3Dpath (KVM device path, default /dev/kvm)\n" + " pmu-cap-disabled=3Dtrue|false (disable KVM_CAP_PMU_CA= PABILITY, x86 only, default false)\n", QEMU_ARCH_ALL) SRST ``-accel name[,prop=3Dvalue[,...]]`` This is used to enable an accelerator. Depending on the target @@ -277,6 +278,12 @@ SRST option can be used to pass the KVM device to use via a file descri= ptor by setting the value to ``/dev/fdset/NN``. =20 + ``pmu-cap-disabled=3Dtrue|false`` + When using the KVM accelerator, it controls the disabling of + KVM_CAP_PMU_CAPABILITY via KVM_PMU_CAP_DISABLE. When this capabili= ty is + disabled, PMU virtualization is turned off at the KVM module level. + Note that this functionality is supported for x86 hosts only. + ERST =20 DEF("smp", HAS_ARG, QEMU_OPTION_smp, diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4490a7a8d6..c97ed74a47 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7102,7 +7102,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, case 0x80000022: *eax =3D *ebx =3D *ecx =3D *edx =3D 0; /* AMD Extended Performance Monitoring and Debug */ - if (kvm_enabled() && cpu->enable_pmu && + if (kvm_enabled() && cpu->enable_pmu && !kvm_pmu_cap_disabled() && (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_PERFCORE) && (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFM= ON_V2)) { *eax |=3D CPUID_8000_0022_EAX_PERFMON_V2; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 8e17942c3b..ed73b1e7e0 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -166,6 +166,7 @@ static bool has_msr_vmx_procbased_ctls2; static bool has_msr_perf_capabs; static bool has_msr_pkrs; static bool has_msr_hwcr; +static bool has_pmu_cap; =20 static uint32_t has_architectural_pmu_version; static uint32_t num_architectural_pmu_gp_counters; @@ -3196,6 +3197,11 @@ static void kvm_vm_enable_energy_msrs(KVMState *s) return; } =20 +bool kvm_pmu_cap_disabled(void) +{ + return kvm_state->pmu_cap_disabled; +} + int kvm_arch_init(MachineState *ms, KVMState *s) { int ret; @@ -3335,6 +3341,23 @@ int kvm_arch_init(MachineState *ms, KVMState *s) } } =20 + has_pmu_cap =3D kvm_check_extension(s, KVM_CAP_PMU_CAPABILITY); + + if (s->pmu_cap_disabled) { + if (has_pmu_cap) { + ret =3D kvm_vm_enable_cap(s, KVM_CAP_PMU_CAPABILITY, 0, + KVM_PMU_CAP_DISABLE); + if (ret < 0) { + s->pmu_cap_disabled =3D false; + error_report("kvm: Failed to disable pmu cap: %s", + strerror(-ret)); + } + } else { + s->pmu_cap_disabled =3D false; + error_report("kvm: KVM_CAP_PMU_CAPABILITY is not supported"); + } + } + return 0; } =20 @@ -6525,6 +6548,29 @@ static void kvm_arch_set_xen_evtchn_max_pirq(Object = *obj, Visitor *v, s->xen_evtchn_max_pirq =3D value; } =20 +static void kvm_set_pmu_cap_disabled(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + KVMState *s =3D KVM_STATE(obj); + bool pmu_cap_disabled; + Error *error =3D NULL; + + if (s->fd !=3D -1) { + error_setg(errp, "Cannot set properties after the accelerator has " + "been initialized"); + return; + } + + visit_type_bool(v, name, &pmu_cap_disabled, &error); + if (error) { + error_propagate(errp, error); + return; + } + + s->pmu_cap_disabled =3D pmu_cap_disabled; +} + void kvm_arch_accel_class_init(ObjectClass *oc) { object_class_property_add_enum(oc, "notify-vmexit", "NotifyVMexitOptio= n", @@ -6564,6 +6610,12 @@ void kvm_arch_accel_class_init(ObjectClass *oc) NULL, NULL); object_class_property_set_description(oc, "xen-evtchn-max-pirq", "Maximum number of Xen PIRQs"); + + object_class_property_add(oc, "pmu-cap-disabled", "bool", + NULL, kvm_set_pmu_cap_disabled, + NULL, NULL); + object_class_property_set_description(oc, "pmu-cap-disabled", + "Disable KVM_CAP_PMU_CAPABILITY"= ); } =20 void kvm_set_max_apic_id(uint32_t max_apic_id) diff --git a/target/i386/kvm/kvm_i386.h b/target/i386/kvm/kvm_i386.h index 9de9c0d303..03522de9d1 100644 --- a/target/i386/kvm/kvm_i386.h +++ b/target/i386/kvm/kvm_i386.h @@ -49,6 +49,8 @@ uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, = uint32_t index); void kvm_set_max_apic_id(uint32_t max_apic_id); void kvm_request_xsave_components(X86CPU *cpu, uint64_t mask); =20 +bool kvm_pmu_cap_disabled(void); + #ifdef CONFIG_KVM =20 bool kvm_is_vm_type_supported(int type); --=20 2.39.3 From nobody Sat Nov 23 20:53:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1730713414; cv=none; d=zohomail.com; s=zohoarc; b=M1sT5euaBBk/qMNE0i0BfYxxrcxb36lWDBu1Jx5cTOtMCQ9GyX4Lx8qKUPupg84FK7UFePKF/WZ4cosKd/Ww5ux5TQ4R3QRQAJdvv1rWO5jaMzwAsPn1kTUOXraovlLbMyL+z3ULnS8vDgW3jUilr0CVWch49y0t0zF+Co20i44= ARC-Message-Signature: i=1; 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charset="utf-8" Currently, the 'has_architectural_pmu_version', 'num_architectural_pmu_gp_counters', and 'num_architectural_pmu_fixed_counters' are shared globally across all vCPUs and are initialized during the setup of each vCPU. To optimize, initialize PMU information only once for the first vCPU. Additionally, the code extracted from kvm_x86_build_cpuid() is unrelated to the process of building the CPUID. Signed-off-by: Dongli Zhang --- target/i386/kvm/kvm.c | 71 +++++++++++++++++++++++++++---------------- 1 file changed, 44 insertions(+), 27 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index ed73b1e7e0..5c0276f889 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1961,33 +1961,6 @@ static uint32_t kvm_x86_build_cpuid(CPUX86State *env, } } =20 - if (limit >=3D 0x0a) { - uint32_t eax, edx; - - cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx); - - has_architectural_pmu_version =3D eax & 0xff; - if (has_architectural_pmu_version > 0) { - num_architectural_pmu_gp_counters =3D (eax & 0xff00) >> 8; - - /* Shouldn't be more than 32, since that's the number of bits - * available in EBX to tell us _which_ counters are available. - * Play it safe. - */ - if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) { - num_architectural_pmu_gp_counters =3D MAX_GP_COUNTERS; - } - - if (has_architectural_pmu_version > 1) { - num_architectural_pmu_fixed_counters =3D edx & 0x1f; - - if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNT= ERS) { - num_architectural_pmu_fixed_counters =3D MAX_FIXED_COU= NTERS; - } - } - } - } - cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); =20 for (i =3D 0x80000000; i <=3D limit; i++) { @@ -2055,6 +2028,43 @@ full: abort(); } =20 +static void kvm_init_pmu_info(CPUX86State *env) +{ + uint32_t eax, edx; + uint32_t unused; + uint32_t limit; + + cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); + + if (limit < 0x0a) { + return; + } + + cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx); + + has_architectural_pmu_version =3D eax & 0xff; + if (has_architectural_pmu_version > 0) { + num_architectural_pmu_gp_counters =3D (eax & 0xff00) >> 8; + + /* + * Shouldn't be more than 32, since that's the number of bits + * available in EBX to tell us _which_ counters are available. + * Play it safe. + */ + if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) { + num_architectural_pmu_gp_counters =3D MAX_GP_COUNTERS; + } + + if (has_architectural_pmu_version > 1) { + num_architectural_pmu_fixed_counters =3D edx & 0x1f; + + if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS)= { + num_architectural_pmu_fixed_counters =3D MAX_FIXED_COUNTER= S; + } + } + } +} + int kvm_arch_init_vcpu(CPUState *cs) { struct { @@ -2237,6 +2247,13 @@ int kvm_arch_init_vcpu(CPUState *cs) cpuid_i =3D kvm_x86_build_cpuid(env, cpuid_data.entries, cpuid_i); cpuid_data.cpuid.nent =3D cpuid_i; =20 + /* + * Initialize PMU information only once for the first vCPU. + */ + if (cs =3D=3D first_cpu) { + kvm_init_pmu_info(env); + } + if (((env->cpuid_version >> 8)&0xF) >=3D 6 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) =3D=3D (CPUID_MCE | CPUID_MCA)) { --=20 2.39.3 From nobody Sat Nov 23 20:53:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2023-11-20; bh=aw8Da KbTFy541Imzo6l3juUlheHXjuaW/lcnjuRi9i8=; b=KQzh8vUimbrwlWWWRQ0bQ Wr2Sa1pd+x5EDv7de0eGJmN7gJ84M+8+oNTQQ5MC9fxVf98M1mmD9zPZPCJ3dP4v zwW4NhdTk1KM36Ijw1ykS6CG51DDB3fXtGGF495iX9SRayQKVZTDLUslP6r9QUL7 qrLW0BRjBSuXIVz1oQnZFaHSPnz3pHExOwX1Ohate/CpqE4UJdjHo1N1qhKil2rs CXf4uU05SabHWvc2Puu5cc7ocxU/d8FHq2DsjTJNVTlntLk8811hKK4QAGqKXNaZ /+/BiNBIddJ4GedmqsF4nsXtQUUBwEW2Eof5oFuGp4LyW0e0ePO2AWhOQfJmWGUO A== From: Dongli Zhang To: qemu-devel@nongnu.org, kvm@vger.kernel.org Cc: pbonzini@redhat.com, mtosatti@redhat.com, sandipan.das@amd.com, babu.moger@amd.com, zhao1.liu@intel.com, likexu@tencent.com, like.xu.linux@gmail.com, zhenyuw@linux.intel.com, groug@kaod.org, lyan@digitalocean.com, khorenko@virtuozzo.com, alexander.ivanov@virtuozzo.com, den@virtuozzo.com, joe.jin@oracle.com, davydov-max@yandex-team.ru Subject: [PATCH 4/7] target/i386/kvm: rename architectural PMU variables Date: Mon, 4 Nov 2024 01:40:19 -0800 Message-ID: <20241104094119.4131-5-dongli.zhang@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20241104094119.4131-1-dongli.zhang@oracle.com> References: <20241104094119.4131-1-dongli.zhang@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-11-04_07,2024-11-01_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 phishscore=0 mlxlogscore=999 mlxscore=0 suspectscore=0 bulkscore=0 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2409260000 definitions=main-2411040085 X-Proofpoint-ORIG-GUID: G2G7tkFTicVLrnW9tFGXNacg0DRyZo-U X-Proofpoint-GUID: G2G7tkFTicVLrnW9tFGXNacg0DRyZo-U Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" AMD does not have what is commonly referred to as an architectural PMU. Therefore, we need to rename the following variables to be applicable for both Intel and AMD: - has_architectural_pmu_version - num_architectural_pmu_gp_counters - num_architectural_pmu_fixed_counters For Intel processors, the meaning of has_pmu_version remains unchanged. For AMD processors: has_pmu_version =3D=3D 1 corresponds to versions before AMD PerfMonV2. has_pmu_version =3D=3D 2 corresponds to AMD PerfMonV2. Signed-off-by: Dongli Zhang --- target/i386/kvm/kvm.c | 49 ++++++++++++++++++++++++------------------- 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 5c0276f889..ca2b644e2c 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -168,9 +168,16 @@ static bool has_msr_pkrs; static bool has_msr_hwcr; static bool has_pmu_cap; =20 -static uint32_t has_architectural_pmu_version; -static uint32_t num_architectural_pmu_gp_counters; -static uint32_t num_architectural_pmu_fixed_counters; +/* + * For Intel processors, the meaning is the architectural PMU version + * number. + * + * For AMD processors: 1 corresponds to the prior versions, and 2 + * corresponds to AMD PerfMonV2. + */ +static uint32_t has_pmu_version; +static uint32_t num_pmu_gp_counters; +static uint32_t num_pmu_fixed_counters; =20 static int has_xsave2; static int has_xcrs; @@ -2042,24 +2049,24 @@ static void kvm_init_pmu_info(CPUX86State *env) =20 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx); =20 - has_architectural_pmu_version =3D eax & 0xff; - if (has_architectural_pmu_version > 0) { - num_architectural_pmu_gp_counters =3D (eax & 0xff00) >> 8; + has_pmu_version =3D eax & 0xff; + if (has_pmu_version > 0) { + num_pmu_gp_counters =3D (eax & 0xff00) >> 8; =20 /* * Shouldn't be more than 32, since that's the number of bits * available in EBX to tell us _which_ counters are available. * Play it safe. */ - if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) { - num_architectural_pmu_gp_counters =3D MAX_GP_COUNTERS; + if (num_pmu_gp_counters > MAX_GP_COUNTERS) { + num_pmu_gp_counters =3D MAX_GP_COUNTERS; } =20 - if (has_architectural_pmu_version > 1) { - num_architectural_pmu_fixed_counters =3D edx & 0x1f; + if (has_pmu_version > 1) { + num_pmu_fixed_counters =3D edx & 0x1f; =20 - if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS)= { - num_architectural_pmu_fixed_counters =3D MAX_FIXED_COUNTER= S; + if (num_pmu_fixed_counters > MAX_FIXED_COUNTERS) { + num_pmu_fixed_counters =3D MAX_FIXED_COUNTERS; } } } @@ -4020,25 +4027,25 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control= _msr); } =20 - if (has_architectural_pmu_version > 0) { - if (has_architectural_pmu_version > 1) { + if (has_pmu_version > 0) { + if (has_pmu_version > 1) { /* Stop the counter. */ kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); } =20 /* Set the counter values. */ - for (i =3D 0; i < num_architectural_pmu_fixed_counters; i++) { + for (i =3D 0; i < num_pmu_fixed_counters; i++) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, env->msr_fixed_counters[i]); } - for (i =3D 0; i < num_architectural_pmu_gp_counters; i++) { + for (i =3D 0; i < num_pmu_gp_counters; i++) { kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, env->msr_gp_counters[i]); kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, env->msr_gp_evtsel[i]); } - if (has_architectural_pmu_version > 1) { + if (has_pmu_version > 1) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, env->msr_global_status); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, @@ -4496,17 +4503,17 @@ static int kvm_get_msrs(X86CPU *cpu) if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) { kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1); } - if (has_architectural_pmu_version > 0) { - if (has_architectural_pmu_version > 1) { + if (has_pmu_version > 0) { + if (has_pmu_version > 1) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0); } - for (i =3D 0; i < num_architectural_pmu_fixed_counters; i++) { + for (i =3D 0; i < num_pmu_fixed_counters; i++) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0); } - for (i =3D 0; i < num_architectural_pmu_gp_counters; i++) { + for (i =3D 0; i < num_pmu_gp_counters; i++) { kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0); kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0); } --=20 2.39.3 From nobody Sat Nov 23 20:53:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 4 Nov 2024 09:42:01 GMT Received: from localhost.localdomain (ca-dev80.us.oracle.com [10.211.9.80]) by iadpaimrmta03.imrmtpd1.prodappiadaev1.oraclevcn.com (PPS) with ESMTP id 42nahbt06k-6; Mon, 04 Nov 2024 09:42:01 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2023-11-20; bh=Iclc0 zYVet4nx97YIS/BP9FtQpieaSXD0nnk1nSLYTE=; b=mhhDRL664Gemhe8XLOnwp y3kTWMYkGSJI+MiKWwFekrw1xofWdDq4XhuB7kEYIUGkSMUMIdjo5tgYsAzhU/1V J43KiAjRc5aUn3o/WRWbyyI2ESAEf2OSDunXQruP1FapEfKsbANLbrTMKx1Jr9L7 ZOkm0mFpT1GPwk7rJnm3k6jS3XtFbHaLdDTaJUUZBzKTX5YcwOP7Ki9NPGL8CSl+ sksldJHzNXmSn5jLRsaKWw7cY95kkLyavvUJDdQe9zGO0Q+Elsb4v0h8GnIaV9KL s/t3QqBTlr0LwEdeXJd8GqVG1oXD+CdipWzkreEIVB3Qy6Zot0jpl9p3eZHoZJNX g== From: Dongli Zhang To: qemu-devel@nongnu.org, kvm@vger.kernel.org Cc: pbonzini@redhat.com, mtosatti@redhat.com, sandipan.das@amd.com, babu.moger@amd.com, zhao1.liu@intel.com, likexu@tencent.com, like.xu.linux@gmail.com, zhenyuw@linux.intel.com, groug@kaod.org, lyan@digitalocean.com, khorenko@virtuozzo.com, alexander.ivanov@virtuozzo.com, den@virtuozzo.com, joe.jin@oracle.com, davydov-max@yandex-team.ru Subject: [PATCH 5/7] target/i386/kvm: reset AMD PMU registers during VM reset Date: Mon, 4 Nov 2024 01:40:20 -0800 Message-ID: <20241104094119.4131-6-dongli.zhang@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20241104094119.4131-1-dongli.zhang@oracle.com> References: <20241104094119.4131-1-dongli.zhang@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-11-04_07,2024-11-01_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 phishscore=0 mlxlogscore=999 mlxscore=0 suspectscore=0 bulkscore=0 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2409260000 definitions=main-2411040085 X-Proofpoint-ORIG-GUID: LGLvVXHmiIkrbiWy_YSBI4nhmM2P3gqK X-Proofpoint-GUID: LGLvVXHmiIkrbiWy_YSBI4nhmM2P3gqK Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" QEMU uses the kvm_get_msrs() function to save Intel PMU registers from KVM and kvm_put_msrs() to restore them to KVM. However, there is no support for AMD PMU registers. Currently, has_pmu_version and num_pmu_gp_counters are initialized based on cpuid(0xa), which does not apply to AMD processors. For AMD CPUs, prior to PerfMonV2, the number of general-purpose registers is determined based on the CPU version. To address this issue, we need to add support for AMD PMU registers. Without this support, the following problems can arise: 1. If the VM is reset (e.g., via QEMU system_reset or VM kdump/kexec) while running "perf top", the PMU registers are not disabled properly. 2. Despite x86_cpu_reset() resetting many registers to zero, kvm_put_msrs() does not handle AMD PMU registers, causing some PMU events to remain enabled in KVM. 3. The KVM kvm_pmc_speculative_in_use() function consistently returns true, preventing the reclamation of these events. Consequently, the kvm_pmc->perf_event remains active. 4. After a reboot, the VM kernel may report the following error: [ 0.092011] Performance Events: Fam17h+ core perfctr, Broken BIOS detect= ed, complain to your hardware vendor. [ 0.092023] [Firmware Bug]: the BIOS has corrupted hw-PMU resources (MSR= c0010200 is 530076) 5. In the worst case, the active kvm_pmc->perf_event may inject unknown NMIs randomly into the VM kernel: [...] Uhhuh. NMI received for unknown reason 30 on CPU 0. To resolve these issues, we propose resetting AMD PMU registers during the VM reset process. Signed-off-by: Dongli Zhang --- target/i386/cpu.h | 8 +++ target/i386/kvm/kvm.c | 156 +++++++++++++++++++++++++++++++++++++++++- 2 files changed, 161 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 59959b8b7a..0505eb3b08 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -488,6 +488,14 @@ typedef enum X86Seg { #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 =20 +#define MSR_K7_EVNTSEL0 0xc0010000 +#define MSR_K7_PERFCTR0 0xc0010004 +#define MSR_F15H_PERF_CTL0 0xc0010200 +#define MSR_F15H_PERF_CTR0 0xc0010201 + +#define AMD64_NUM_COUNTERS 4 +#define AMD64_NUM_COUNTERS_CORE 6 + #define MSR_MC0_CTL 0x400 #define MSR_MC0_STATUS 0x401 #define MSR_MC0_ADDR 0x402 diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index ca2b644e2c..83ec85a9b9 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2035,7 +2035,7 @@ full: abort(); } =20 -static void kvm_init_pmu_info(CPUX86State *env) +static void kvm_init_pmu_info_intel(CPUX86State *env) { uint32_t eax, edx; uint32_t unused; @@ -2072,6 +2072,80 @@ static void kvm_init_pmu_info(CPUX86State *env) } } =20 +static void kvm_init_pmu_info_amd(CPUX86State *env) +{ + int64_t family; + + has_pmu_version =3D 0; + + /* + * To determine the CPU family, the following code is derived from + * x86_cpuid_version_get_family(). + */ + family =3D (env->cpuid_version >> 8) & 0xf; + if (family =3D=3D 0xf) { + family +=3D (env->cpuid_version >> 20) & 0xff; + } + + /* + * Performance-monitoring supported from K7 and later. + */ + if (family < 6) { + return; + } + + has_pmu_version =3D 1; + + if (!(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_PERFCORE)) { + num_pmu_gp_counters =3D AMD64_NUM_COUNTERS; + return; + } + + num_pmu_gp_counters =3D AMD64_NUM_COUNTERS_CORE; +} + +static bool is_same_vendor(CPUX86State *env) +{ + static uint32_t host_cpuid_vendor1; + static uint32_t host_cpuid_vendor2; + static uint32_t host_cpuid_vendor3; + + host_cpuid(0x0, 0, NULL, &host_cpuid_vendor1, &host_cpuid_vendor3, + &host_cpuid_vendor2); + + return env->cpuid_vendor1 =3D=3D host_cpuid_vendor1 && + env->cpuid_vendor2 =3D=3D host_cpuid_vendor2 && + env->cpuid_vendor3 =3D=3D host_cpuid_vendor3; +} + +static void kvm_init_pmu_info(CPUX86State *env) +{ + /* + * It is not supported to virtualize AMD PMU registers on Intel + * processors, nor to virtualize Intel PMU registers on AMD processors. + */ + if (!is_same_vendor(env)) { + return; + } + + /* + * If KVM_CAP_PMU_CAPABILITY is not supported, there is no way to + * disable the AMD pmu virtualization. + * + * If KVM_CAP_PMU_CAPABILITY is supported, kvm_state->pmu_cap_disabled + * indicates the KVM has already disabled the pmu virtualization. + */ + if (kvm_state->pmu_cap_disabled) { + return; + } + + if (IS_INTEL_CPU(env)) { + kvm_init_pmu_info_intel(env); + } else if (IS_AMD_CPU(env)) { + kvm_init_pmu_info_amd(env); + } +} + int kvm_arch_init_vcpu(CPUState *cs) { struct { @@ -4027,7 +4101,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control= _msr); } =20 - if (has_pmu_version > 0) { + if (IS_INTEL_CPU(env) && has_pmu_version > 0) { if (has_pmu_version > 1) { /* Stop the counter. */ kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); @@ -4058,6 +4132,38 @@ static int kvm_put_msrs(X86CPU *cpu, int level) env->msr_global_ctrl); } } + + if (IS_AMD_CPU(env) && has_pmu_version > 0) { + uint32_t sel_base =3D MSR_K7_EVNTSEL0; + uint32_t ctr_base =3D MSR_K7_PERFCTR0; + /* + * The address of the next selector or counter register is + * obtained by incrementing the address of the current selector + * or counter register by one. + */ + uint32_t step =3D 1; + + /* + * When PERFCORE is enabled, AMD PMU uses a separate set of + * addresses for the selector and counter registers. + * Additionally, the address of the next selector or counter + * register is determined by incrementing the address of the + * current register by two. + */ + if (num_pmu_gp_counters =3D=3D AMD64_NUM_COUNTERS_CORE) { + sel_base =3D MSR_F15H_PERF_CTL0; + ctr_base =3D MSR_F15H_PERF_CTR0; + step =3D 2; + } + + for (i =3D 0; i < num_pmu_gp_counters; i++) { + kvm_msr_entry_add(cpu, ctr_base + i * step, + env->msr_gp_counters[i]); + kvm_msr_entry_add(cpu, sel_base + i * step, + env->msr_gp_evtsel[i]); + } + } + /* * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-= add, * only sync them to KVM on the first cpu @@ -4503,7 +4609,8 @@ static int kvm_get_msrs(X86CPU *cpu) if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) { kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1); } - if (has_pmu_version > 0) { + + if (IS_INTEL_CPU(env) && has_pmu_version > 0) { if (has_pmu_version > 1) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); @@ -4519,6 +4626,35 @@ static int kvm_get_msrs(X86CPU *cpu) } } =20 + if (IS_AMD_CPU(env) && has_pmu_version > 0) { + uint32_t sel_base =3D MSR_K7_EVNTSEL0; + uint32_t ctr_base =3D MSR_K7_PERFCTR0; + /* + * The address of the next selector or counter register is + * obtained by incrementing the address of the current selector + * or counter register by one. + */ + uint32_t step =3D 1; + + /* + * When PERFCORE is enabled, AMD PMU uses a separate set of + * addresses for the selector and counter registers. + * Additionally, the address of the next selector or counter + * register is determined by incrementing the address of the + * current register by two. + */ + if (num_pmu_gp_counters =3D=3D AMD64_NUM_COUNTERS_CORE) { + sel_base =3D MSR_F15H_PERF_CTL0; + ctr_base =3D MSR_F15H_PERF_CTR0; + step =3D 2; + } + + for (i =3D 0; i < num_pmu_gp_counters; i++) { + kvm_msr_entry_add(cpu, ctr_base + i * step, 0); + kvm_msr_entry_add(cpu, sel_base + i * step, 0); + } + } + if (env->mcg_cap) { kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0); kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0); @@ -4830,6 +4966,20 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] =3D msrs[i].data; break; + case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL0 + 3: + env->msr_gp_evtsel[index - MSR_K7_EVNTSEL0] =3D msrs[i].data; + break; + case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR0 + 3: + env->msr_gp_counters[index - MSR_K7_PERFCTR0] =3D msrs[i].data; + break; + case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTL0 + 0xb: + index =3D index - MSR_F15H_PERF_CTL0; + if (index & 0x1) { + env->msr_gp_counters[index] =3D msrs[i].data; + } else { + env->msr_gp_evtsel[index] =3D msrs[i].data; + } + break; case HV_X64_MSR_HYPERCALL: env->msr_hv_hypercall =3D msrs[i].data; break; --=20 2.39.3 From nobody Sat Nov 23 20:53:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1730713397; cv=none; d=zohomail.com; s=zohoarc; b=gw3ow1V8GtVe5lpwYYNXQb+cFXHWa6LsUpKGylznCO+vXhEmMJqKYRPcg4ynncJXaEe/60ojR0ZWECWiWkVgZdrkpkr5IhuC5as/AjHHNvPTiVKi0Rs9YbCAIi3VI32lPaOnfsHPmtqrrT5k+H7wkRhiYtVSONFIO3UcX9Fq1SU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730713397; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Since perfmon-v2, the AMD PMU supports additional registers. This update includes get/put functionality for these extra registers. Similar to the implementation in KVM: - MSR_CORE_PERF_GLOBAL_STATUS and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS both use env->msr_global_status. - MSR_CORE_PERF_GLOBAL_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_CTL both use env->msr_global_ctrl. - MSR_CORE_PERF_GLOBAL_OVF_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR both use env->msr_global_ovf_ctrl. No changes are needed for vmstate_msr_architectural_pmu or pmu_enable_needed(). Signed-off-by: Dongli Zhang --- target/i386/cpu.h | 4 ++++ target/i386/kvm/kvm.c | 47 ++++++++++++++++++++++++++++++++++--------- 2 files changed, 42 insertions(+), 9 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0505eb3b08..68ed798808 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -488,6 +488,10 @@ typedef enum X86Seg { #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 =20 +#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 +#define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 +#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 + #define MSR_K7_EVNTSEL0 0xc0010000 #define MSR_K7_PERFCTR0 0xc0010004 #define MSR_F15H_PERF_CTL0 0xc0010200 diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 83ec85a9b9..918dcb61fe 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2074,6 +2074,8 @@ static void kvm_init_pmu_info_intel(CPUX86State *env) =20 static void kvm_init_pmu_info_amd(CPUX86State *env) { + uint32_t eax, ebx; + uint32_t unused; int64_t family; =20 has_pmu_version =3D 0; @@ -2102,6 +2104,13 @@ static void kvm_init_pmu_info_amd(CPUX86State *env) } =20 num_pmu_gp_counters =3D AMD64_NUM_COUNTERS_CORE; + + cpu_x86_cpuid(env, 0x80000022, 0, &eax, &ebx, &unused, &unused); + + if (eax & CPUID_8000_0022_EAX_PERFMON_V2) { + has_pmu_version =3D 2; + num_pmu_gp_counters =3D ebx & 0xf; + } } =20 static bool is_same_vendor(CPUX86State *env) @@ -4144,13 +4153,14 @@ static int kvm_put_msrs(X86CPU *cpu, int level) uint32_t step =3D 1; =20 /* - * When PERFCORE is enabled, AMD PMU uses a separate set of - * addresses for the selector and counter registers. - * Additionally, the address of the next selector or counter - * register is determined by incrementing the address of the - * current register by two. + * When PERFCORE or PerfMonV2 is enabled, AMD PMU uses a + * separate set of addresses for the selector and counter + * registers. Additionally, the address of the next selector or + * counter register is determined by incrementing the address + * of the current register by two. */ - if (num_pmu_gp_counters =3D=3D AMD64_NUM_COUNTERS_CORE) { + if (num_pmu_gp_counters =3D=3D AMD64_NUM_COUNTERS_CORE || + has_pmu_version =3D=3D 2) { sel_base =3D MSR_F15H_PERF_CTL0; ctr_base =3D MSR_F15H_PERF_CTR0; step =3D 2; @@ -4162,6 +4172,15 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_add(cpu, sel_base + i * step, env->msr_gp_evtsel[i]); } + + if (has_pmu_version =3D=3D 2) { + kvm_msr_entry_add(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, + env->msr_global_status); + kvm_msr_entry_add(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_C= LR, + env->msr_global_ovf_ctrl); + kvm_msr_entry_add(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_CTL, + env->msr_global_ctrl); + } } =20 /* @@ -4637,13 +4656,14 @@ static int kvm_get_msrs(X86CPU *cpu) uint32_t step =3D 1; =20 /* - * When PERFCORE is enabled, AMD PMU uses a separate set of - * addresses for the selector and counter registers. + * When PERFCORE or PerfMonV2 is enabled, AMD PMU uses a separate + * set of addresses for the selector and counter registers. * Additionally, the address of the next selector or counter * register is determined by incrementing the address of the * current register by two. */ - if (num_pmu_gp_counters =3D=3D AMD64_NUM_COUNTERS_CORE) { + if (num_pmu_gp_counters =3D=3D AMD64_NUM_COUNTERS_CORE || + has_pmu_version =3D=3D 2) { sel_base =3D MSR_F15H_PERF_CTL0; ctr_base =3D MSR_F15H_PERF_CTR0; step =3D 2; @@ -4653,6 +4673,12 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, ctr_base + i * step, 0); kvm_msr_entry_add(cpu, sel_base + i * step, 0); } + + if (has_pmu_version =3D=3D 2) { + kvm_msr_entry_add(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0); + kvm_msr_entry_add(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, 0); + kvm_msr_entry_add(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, = 0); + } } =20 if (env->mcg_cap) { @@ -4949,12 +4975,15 @@ static int kvm_get_msrs(X86CPU *cpu) env->msr_fixed_ctr_ctrl =3D msrs[i].data; break; case MSR_CORE_PERF_GLOBAL_CTRL: + case MSR_AMD64_PERF_CNTR_GLOBAL_CTL: env->msr_global_ctrl =3D msrs[i].data; break; case MSR_CORE_PERF_GLOBAL_STATUS: + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: env->msr_global_status =3D msrs[i].data; break; case MSR_CORE_PERF_GLOBAL_OVF_CTRL: + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: env->msr_global_ovf_ctrl =3D msrs[i].data; break; case MSR_CORE_PERF_FIXED_CTR0 ... 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charset="utf-8" The kvm_put_msrs() sets the MSRs using KVM_SET_MSRS. The x86 KVM processes these MSRs one by one in a loop, only saving the config and triggering the KVM_REQ_PMU request. This approach does not immediately stop the event before updating PMC. In additional, PMU MSRs are set only at levels >=3D KVM_PUT_RESET_STATE, excluding runtime. Therefore, updating these MSRs without stopping events should be acceptable. Finally, KVM creates kernel perf events with host mode excluded (exclude_host =3D 1). While the events remain active, they don't increment the counter during QEMU vCPU userspace mode. No Fixed tag is going to be added for the commit 0d89436786b0 ("kvm: migrate vPMU state"), because this isn't a bugfix. Signed-off-by: Dongli Zhang --- target/i386/kvm/kvm.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 918dcb61fe..c4a11c2e80 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4111,13 +4111,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level) } =20 if (IS_INTEL_CPU(env) && has_pmu_version > 0) { - if (has_pmu_version > 1) { - /* Stop the counter. */ - kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); - kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); - } - - /* Set the counter values. */ for (i =3D 0; i < num_pmu_fixed_counters; i++) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, env->msr_fixed_counters[i]); @@ -4133,8 +4126,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level) env->msr_global_status); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, env->msr_global_ovf_ctrl); - - /* Now start the PMU. */ kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, env->msr_fixed_ctr_ctrl); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, --=20 2.39.3