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Mon, 4 Nov 2024 06:43:41 +0000 (GMT) Received: from smtpav06.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 647C95803F; Mon, 4 Nov 2024 06:43:41 +0000 (GMT) Received: from gfwa829.aus.stglabs.ibm.com (unknown [9.3.84.19]) by smtpav06.wdc07v.mail.ibm.com (Postfix) with ESMTP; Mon, 4 Nov 2024 06:43:41 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pp1; bh=12xXlt YqF+5NA+UACUM0PbtxD105v5LqQL+TvOsHFrc=; b=Uh0mTgli3lr9TvbqJpTlkW yZipx/jdwjXm43tV7akk/R2Rvbt0cZF0XnzYUmjs61tw1Bbhal8nfitcizP6x0hJ 886k5GOvzFJevlznjHXcW/VrBYQIzaJqjizJQhIOaJci+8BX/DkDaDNJtpAdkC30 f3BShapKiA79+wZDauMQLUDgReV0Y3icxeiT/2f5fXYgtlCvZeGLJbQwlzgoXCJh gK7jsnGvOG56ZaZm4mCb9ccNqNNzfWc+0cmWuK1tPcKwt3knJaQG/Mu3HdULwHkt rwIQNmA/vyDerF/YjoaQXqrRkiFFUo03ossEyumaAUbkHs6vuPLzoe3FZA8CxRPQ == From: dan tan To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, stefanb@linux.vnet.ibm.com, pbonzini@redhat.com, farosas@suse.de, lvivier@redhat.com, clg@kaod.org, dantan@linux.ibm.com Subject: [PATCH v5 1/3] tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface) Date: Mon, 4 Nov 2024 00:43:32 -0600 Message-Id: <20241104064334.21468-2-dantan@linux.vnet.ibm.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241104064334.21468-1-dantan@linux.vnet.ibm.com> References: <20241104064334.21468-1-dantan@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Nyr6gN9fq8NCSS_7XWXrn0OGP4DgEPkW X-Proofpoint-GUID: Nyr6gN9fq8NCSS_7XWXrn0OGP4DgEPkW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 suspectscore=0 priorityscore=1501 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411040057 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=148.163.158.5; envelope-from=dantan@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1730702711488116600 Implement support for TPM via SPI interface. The SPI bus master is provided by PowerNV SPI device which is an SSI peripheral. It can uses the tpm_emulator driver backend with the external swtpm. Although the implementation is endian neutral, the SPI bus master provider, pnv_spi.c is only supported on the PowerNV platform, thus, is big endian specific. Signed-off-by: dan tan --- v3: - moved variable tis_addr from TPMStateSPI struct to local - added the VM suspend/resume support: - added vmstate_tpm_tis_spi declaration - added tpm_tis_spi_pre_save() function - fixed trace formatting string v4: - git commit amend only v5: - removed DEFINE_PROP_UINT32("irq", TPMStateSPI, tpm_state.irq_num, 0) from tpm_tis_spi_properties - In tpm.rst document, under section 'The QEMU TPM emulator device', moved the 'PowerNV machine' section to immeidately below 'pSeriese machine'. --- docs/specs/tpm.rst | 15 ++ include/sysemu/tpm.h | 3 + hw/tpm/tpm_tis_spi.c | 359 +++++++++++++++++++++++++++++++++++++++++++ hw/tpm/Kconfig | 6 + hw/tpm/meson.build | 1 + hw/tpm/trace-events | 7 + 6 files changed, 391 insertions(+) create mode 100644 hw/tpm/tpm_tis_spi.c diff --git a/docs/specs/tpm.rst b/docs/specs/tpm.rst index 1ad36ad709..d92e7eed6f 100644 --- a/docs/specs/tpm.rst +++ b/docs/specs/tpm.rst @@ -24,6 +24,7 @@ QEMU files related to TPM TIS interface: - ``hw/tpm/tpm_tis_isa.c`` - ``hw/tpm/tpm_tis_sysbus.c`` - ``hw/tpm/tpm_tis_i2c.c`` + - ``hw/tpm/tpm_tis_spi.c`` - ``hw/tpm/tpm_tis.h`` =20 Both an ISA device and a sysbus device are available. The former is @@ -33,6 +34,9 @@ Arm virt machine. An I2C device support is also provided which can be instantiated in the Arm based emulation machines. This device only supports the TPM 2 protocol. =20 +A Serial Peripheral Interface (SPI) device support has been added to the +PowerNV emulation machines. This device only supports the TPM 2 protocol. + CRB interface ------------- =20 @@ -339,6 +343,17 @@ In case a pSeries machine is emulated, use the followi= ng command line: -device virtio-blk-pci,bus=3Dpci.0,addr=3D0x3,drive=3Ddrive-virtio-dis= k0,id=3Dvirtio-disk0 \ -drive file=3Dtest.img,format=3Draw,if=3Dnone,id=3Ddrive-virtio-disk0 =20 +In case a PowerNV machine is emulated and you want to use a TPM device +attached to SPI bus, use the following command line (SPI bus master is +provided by PowerNV SPI device): + +.. code-block:: console + + qemu-system-ppc64 -m 2G -machine powernv10 -nographic \ + -chardev socket,id=3Dchrtpm,path=3D/tmp/mytpm1/swtpm-sock \ + -tpmdev emulator,id=3Dtpm0,chardev=3Dchrtpm \ + -device tpm-tis-spi,tpmdev=3Dtpm0,bus=3Dpnv-spi-bus.4 + In case an Arm virt machine is emulated, use the following command line: =20 .. code-block:: console diff --git a/include/sysemu/tpm.h b/include/sysemu/tpm.h index 1ee568b3b6..22b05110e2 100644 --- a/include/sysemu/tpm.h +++ b/include/sysemu/tpm.h @@ -49,6 +49,7 @@ struct TPMIfClass { #define TYPE_TPM_CRB "tpm-crb" #define TYPE_TPM_SPAPR "tpm-spapr" #define TYPE_TPM_TIS_I2C "tpm-tis-i2c" +#define TYPE_TPM_TIS_SPI "tpm-tis-spi" =20 #define TPM_IS_TIS_ISA(chr) \ object_dynamic_cast(OBJECT(chr), TYPE_TPM_TIS_ISA) @@ -60,6 +61,8 @@ struct TPMIfClass { object_dynamic_cast(OBJECT(chr), TYPE_TPM_SPAPR) #define TPM_IS_TIS_I2C(chr) \ object_dynamic_cast(OBJECT(chr), TYPE_TPM_TIS_I2C) +#define TPM_IS_TIS_SPI(chr) \ + object_dynamic_cast(OBJECT(chr), TYPE_TPM_TIS_SPI) =20 /* returns NULL unless there is exactly one TPM device */ static inline TPMIf *tpm_find(void) diff --git a/hw/tpm/tpm_tis_spi.c b/hw/tpm/tpm_tis_spi.c new file mode 100644 index 0000000000..87acbaaaf8 --- /dev/null +++ b/hw/tpm/tpm_tis_spi.c @@ -0,0 +1,359 @@ +/* + * QEMU PowerPC SPI TPM 2.0 model + * + * Copyright (c) 2024, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#define IBM_PONQ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/sysbus.h" +#include "hw/acpi/tpm.h" +#include "tpm_prop.h" +#include "qemu/log.h" +#include "trace.h" +#include "tpm_tis.h" +#include "hw/ssi/ssi.h" +#include "migration/vmstate.h" + +typedef struct TPMStateSPI { + /*< private >*/ + SSIPeripheral parent_object; + + uint8_t byte_offset; /* byte offset in transfer */ + uint8_t wait_state_cnt; /* wait state counter */ + uint8_t xfer_size; /* data size of transfer */ + uint32_t reg_addr; /* register address of transfer */ + + uint8_t spi_state; /* READ / WRITE / IDLE */ +#define SPI_STATE_IDLE 0 +#define SPI_STATE_WRITE 1 +#define SPI_STATE_READ 2 + + bool command; + + /*< public >*/ + TPMState tpm_state; /* not a QOM object */ + +} TPMStateSPI; + +#define CMD_BYTE_WRITE (1 << 7) +#define CMD_BYTE_XFER_SZ_MASK 0x1f +#define TIS_SPI_HIGH_ADDR_BYTE 0xd4 + +DECLARE_INSTANCE_CHECKER(TPMStateSPI, TPM_TIS_SPI, TYPE_TPM_TIS_SPI) + +static int tpm_tis_spi_pre_save(void *opaque) +{ + TPMStateSPI *spist =3D opaque; + + return tpm_tis_pre_save(&spist->tpm_state); +} + +static const VMStateDescription vmstate_tpm_tis_spi =3D { + .name =3D "tpm-tis-spi", + .version_id =3D 0, + .pre_save =3D tpm_tis_spi_pre_save, + .fields =3D (const VMStateField[]) { + VMSTATE_BUFFER(tpm_state.buffer, TPMStateSPI), + VMSTATE_UINT16(tpm_state.rw_offset, TPMStateSPI), + VMSTATE_UINT8(tpm_state.active_locty, TPMStateSPI), + VMSTATE_UINT8(tpm_state.aborting_locty, TPMStateSPI), + VMSTATE_UINT8(tpm_state.next_locty, TPMStateSPI), + + VMSTATE_STRUCT_ARRAY(tpm_state.loc, TPMStateSPI, + TPM_TIS_NUM_LOCALITIES, 0, + vmstate_locty, TPMLocality), + + /* spi specifics */ + VMSTATE_UINT8(byte_offset, TPMStateSPI), + VMSTATE_UINT8(wait_state_cnt, TPMStateSPI), + VMSTATE_UINT8(xfer_size, TPMStateSPI), + VMSTATE_UINT32(reg_addr, TPMStateSPI), + VMSTATE_UINT8(spi_state, TPMStateSPI), + VMSTATE_BOOL(command, TPMStateSPI), + + VMSTATE_END_OF_LIST() + } +}; + +static inline void tpm_tis_spi_clear_data(TPMStateSPI *spist) +{ + spist->spi_state =3D SPI_STATE_IDLE; + spist->byte_offset =3D 0; + spist->wait_state_cnt =3D 0; + spist->xfer_size =3D 0; + spist->reg_addr =3D 0; + + return; +} + +/* Callback from TPM to indicate that response is copied */ +static void tpm_tis_spi_request_completed(TPMIf *ti, int ret) +{ + TPMStateSPI *spist =3D TPM_TIS_SPI(ti); + TPMState *s =3D &spist->tpm_state; + + /* Inform the common code. */ + tpm_tis_request_completed(s, ret); +} + +static enum TPMVersion tpm_tis_spi_get_tpm_version(TPMIf *ti) +{ + TPMStateSPI *spist =3D TPM_TIS_SPI(ti); + TPMState *s =3D &spist->tpm_state; + + return tpm_tis_get_tpm_version(s); +} + +/* + * TCG PC Client Platform TPM Profile Specification for TPM 2.0 ver 1.05 r= ev 14 + * + * For system Software, the TPM has a 64-bit address of 0x0000_0000_FED4_x= xxx. + * On SPI, the chipset passes the least significant 24 bits to the TPM. + * The upper bytes will be used by the chipset to select the TPM=E2=80=99s= SPI CS# + * signal. Table 9 shows the locality based on the 16 least significant ad= dress + * bits and assume that either the LPC TPM sync or SPI TPM CS# is used. + * + */ +static void tpm_tis_spi_write(TPMStateSPI *spist, uint32_t addr, uint8_t v= al) +{ + TPMState *tpm_st =3D &spist->tpm_state; + + trace_tpm_tis_spi_write(addr, val); + tpm_tis_write_data(tpm_st, addr, val, 1); +} + +static uint8_t tpm_tis_spi_read(TPMStateSPI *spist, uint32_t addr) +{ + TPMState *tpm_st =3D &spist->tpm_state; + uint8_t data; + + data =3D tpm_tis_read_data(tpm_st, addr, 1); + trace_tpm_tis_spi_read(addr, data); + return data; +} + +static Property tpm_tis_spi_properties[] =3D { + DEFINE_PROP_TPMBE("tpmdev", TPMStateSPI, tpm_state.be_driver), + DEFINE_PROP_END_OF_LIST(), +}; + +static void tpm_tis_spi_reset(DeviceState *dev) +{ + TPMStateSPI *spist =3D TPM_TIS_SPI(dev); + TPMState *s =3D &spist->tpm_state; + + tpm_tis_spi_clear_data(spist); + return tpm_tis_reset(s); +} + +static uint32_t tpm_transfer(SSIPeripheral *ss, uint32_t tx) +{ + TPMStateSPI *spist =3D TPM_TIS_SPI(ss); + uint32_t rx =3D 0; + uint8_t byte; /* reversed byte value */ + uint8_t offset =3D 0; /* offset of byte in payload */ + uint8_t index; /* index of data byte in transfer */ + uint32_t tis_addr; /* tis address including locty */ + + /* new transfer or not */ + if (spist->command) { /* new transfer start */ + if (spist->spi_state !=3D SPI_STATE_IDLE) { + qemu_log_mask(LOG_GUEST_ERROR, "unexpected new transfer\n"); + } + spist->byte_offset =3D 0; + spist->wait_state_cnt =3D 0; + } + /* + * Explanation of wait_state: + * The original TPM model did not have wait state or "flow control" su= pport + * built in. If you wanted to read a TPM register through SPI you sent + * the first byte with the read/write bit and size, then three address= bytes + * and any additional bytes after that were don't care bytes for reads= and + * the model would begin returning byte data to the SPI reader from the + * register address provided. In the real world this would mean that a + * TPM device had only the time between the 31st clock and the 32nd cl= ock + * to fetch the register data that it had to provide to SPI MISO start= ing + * with the 32nd clock. + * + * In reality the TPM begins introducing a wait state at the 31st clock + * by holding MISO low. This is how it controls the "flow" of the + * operation. Once the data the TPM needs to return is ready it will + * select bit 31 + (8*N) to send back a 1 which indicates that it will + * now start returning data on MISO. + * + * The same wait states are applied to writes. In either the read or = write + * case the wait state occurs between the command+address (4 bytes) an= d the + * data (1-n bytes) sections of the SPI frame. The code below introdu= ces + * the support for a 32 bit wait state for P10. All reads and writes + * through the SPI interface MUST now be aware of the need to do flow + * control in order to use the TPM via SPI. + * + * In conjunction with these changes there were changes made to the SP= IM + * engine that was introduced in P10 to support the 6x op code which is + * used to receive wait state 0s on the MISO line until it sees the b'= 1' + * come back before continuing to read real data from the SPI device(T= PM). + */ + + trace_tpm_tis_spi_transfer_data("Payload byte_offset", spist->byte_off= set); + /* process payload data */ + while (offset < 4) { + spist->command =3D false; + byte =3D (tx >> (24 - 8 * offset)) & 0xFF; + trace_tpm_tis_spi_transfer_data("Extracted byte", byte); + trace_tpm_tis_spi_transfer_data("Payload offset", offset); + switch (spist->byte_offset) { + case 0: /* command byte */ + if ((byte & CMD_BYTE_WRITE) =3D=3D 0) { /* bit-7 */ + spist->spi_state =3D SPI_STATE_WRITE; + trace_tpm_tis_spi_transfer_event("spi write"); + } else { + spist->spi_state =3D SPI_STATE_READ; + trace_tpm_tis_spi_transfer_event("spi read"); + } + spist->xfer_size =3D (byte & CMD_BYTE_XFER_SZ_MASK) + 1; + trace_tpm_tis_spi_transfer_data("xfer_size", spist->xfer_size); + break; + case 1: /* 1st address byte */ + if (byte !=3D TIS_SPI_HIGH_ADDR_BYTE) { + qemu_log_mask(LOG_GUEST_ERROR, "incorrect high address 0x%= x\n", + byte); + } + spist->reg_addr =3D byte << 16; + trace_tpm_tis_spi_transfer_data("first addr byte", byte); + trace_tpm_tis_spi_transfer_addr("reg_addr", spist->reg_addr); + break; + case 2: /* 2nd address byte */ + spist->reg_addr |=3D byte << 8; + trace_tpm_tis_spi_transfer_data("second addr byte", byte); + trace_tpm_tis_spi_transfer_addr("reg_addr", spist->reg_addr); + break; + case 3: /* 3rd address byte */ + spist->reg_addr |=3D byte; + trace_tpm_tis_spi_transfer_data("third addr byte", byte); + trace_tpm_tis_spi_transfer_addr("reg_addr", spist->reg_addr); + break; + default: /* data bytes */ + if (spist->wait_state_cnt < 4) { + spist->wait_state_cnt++; + if (spist->wait_state_cnt =3D=3D 4) { + trace_tpm_tis_spi_transfer_data("wait complete, count", + spist->wait_state_cnt= ); + rx =3D rx | (0x01 << (24 - offset * 8)); + return rx; + } else { + trace_tpm_tis_spi_transfer_data("in wait state, count", + spist->wait_state_cnt= ); + rx =3D 0; + } + } else { + index =3D spist->byte_offset - 4; + trace_tpm_tis_spi_transfer_data("index", index); + trace_tpm_tis_spi_transfer_data("data byte", byte); + trace_tpm_tis_spi_transfer_addr("reg_addr", spist->reg_add= r); + if (index >=3D spist->xfer_size) { + /* + * SPI SSI framework limits both rx and tx + * to fixed 4-byte with each xfer + */ + trace_tpm_tis_spi_transfer_event("index exceeds xfer_s= ize"); + return rx; + } + tis_addr =3D spist->reg_addr + (index % 4); + if (spist->spi_state =3D=3D SPI_STATE_WRITE) { + tpm_tis_spi_write(spist, tis_addr, byte); + } else { + byte =3D tpm_tis_spi_read(spist, tis_addr); + rx =3D rx | (byte << (24 - offset * 8)); + trace_tpm_tis_spi_transfer_data("byte added to respons= e", + byte); + trace_tpm_tis_spi_transfer_data("offset", offset); + } + } + break; + } + if ((spist->wait_state_cnt =3D=3D 0) || (spist->wait_state_cnt =3D= =3D 4)) { + offset++; + spist->byte_offset++; + } else { + break; + } + } + return rx; +} + +static int tpm_cs(SSIPeripheral *ss, bool select) +{ + TPMStateSPI *spist =3D TPM_TIS_SPI(ss); + + if (select) { + spist->command =3D false; + spist->spi_state =3D SPI_STATE_IDLE; + } else { + spist->command =3D true; + } + return 0; +} + +static void tpm_realize(SSIPeripheral *dev, Error **errp) +{ + TPMStateSPI *spist =3D TPM_TIS_SPI(dev); + TPMState *s =3D &spist->tpm_state; + + if (!tpm_find()) { + error_setg(errp, "at most one TPM device is permitted"); + return; + } + + s->be_driver =3D qemu_find_tpm_be("tpm0"); + + if (!s->be_driver) { + error_setg(errp, "unable to find tpm backend device"); + return; + } +} + +static void tpm_tis_spi_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + TPMIfClass *tc =3D TPM_IF_CLASS(klass); + SSIPeripheralClass *k =3D SSI_PERIPHERAL_CLASS(klass); + + k->transfer =3D tpm_transfer; + k->realize =3D tpm_realize; + k->set_cs =3D tpm_cs; + k->cs_polarity =3D SSI_CS_LOW; + + device_class_set_legacy_reset(dc, tpm_tis_spi_reset); + device_class_set_props(dc, tpm_tis_spi_properties); + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + + dc->desc =3D "SPI TPM"; + dc->vmsd =3D &vmstate_tpm_tis_spi; + + tc->model =3D TPM_MODEL_TPM_TIS; + tc->request_completed =3D tpm_tis_spi_request_completed; + tc->get_version =3D tpm_tis_spi_get_tpm_version; +} + +static const TypeInfo tpm_tis_spi_info =3D { + .name =3D TYPE_TPM_TIS_SPI, + .parent =3D TYPE_SSI_PERIPHERAL, + .instance_size =3D sizeof(TPMStateSPI), + .class_init =3D tpm_tis_spi_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_TPM_IF }, + { } + } +}; + +static void tpm_tis_spi_register_types(void) +{ + type_register_static(&tpm_tis_spi_info); +} + +type_init(tpm_tis_spi_register_types) diff --git a/hw/tpm/Kconfig b/hw/tpm/Kconfig index a46663288c..5951c225cc 100644 --- a/hw/tpm/Kconfig +++ b/hw/tpm/Kconfig @@ -5,6 +5,12 @@ config TPM_TIS_I2C select I2C select TPM_TIS =20 +config TPM_TIS_SPI + bool + depends on TPM + select TPM_BACKEND + select TPM_TIS + config TPM_TIS_ISA bool depends on TPM && ISA_BUS diff --git a/hw/tpm/meson.build b/hw/tpm/meson.build index 6968e60b3f..e03cfb11b9 100644 --- a/hw/tpm/meson.build +++ b/hw/tpm/meson.build @@ -2,6 +2,7 @@ system_ss.add(when: 'CONFIG_TPM_TIS', if_true: files('tpm_t= is_common.c')) system_ss.add(when: 'CONFIG_TPM_TIS_ISA', if_true: files('tpm_tis_isa.c')) system_ss.add(when: 'CONFIG_TPM_TIS_SYSBUS', if_true: files('tpm_tis_sysbu= s.c')) system_ss.add(when: 'CONFIG_TPM_TIS_I2C', if_true: files('tpm_tis_i2c.c')) +system_ss.add(when: 'CONFIG_TPM_TIS_SPI', if_true: files('tpm_tis_spi.c')) system_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_crb.c')) system_ss.add(when: 'CONFIG_TPM_TIS', if_true: files('tpm_ppi.c')) system_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_ppi.c')) diff --git a/hw/tpm/trace-events b/hw/tpm/trace-events index fa882dfefe..0324ceb6d0 100644 --- a/hw/tpm/trace-events +++ b/hw/tpm/trace-events @@ -42,3 +42,10 @@ tpm_tis_i2c_recv(uint8_t data) "TPM I2C read: 0x%X" tpm_tis_i2c_send(uint8_t data) "TPM I2C write: 0x%X" tpm_tis_i2c_event(const char *event) "TPM I2C event: %s" tpm_tis_i2c_send_reg(const char *name, int reg) "TPM I2C write register: %= s(0x%X)" + +# tpm_tis_spi.c +tpm_tis_spi_write(uint32_t addr, uint8_t val) "TPM SPI write - addr:0x%08X= 0x%02x" +tpm_tis_spi_read(uint32_t addr, uint8_t val) "TPM SPI read - addr:0x%08X 0= x%02x" +tpm_tis_spi_transfer_event(const char *event) "TPM SPI XFER event: %s" +tpm_tis_spi_transfer_data(const char *name, uint8_t val) "TPM SPI XFER: %s= =3D 0x%02x" +tpm_tis_spi_transfer_addr(const char *name, uint32_t addr) "TPM SPI XFER: = %s =3D 0x%08x" --=20 2.39.5 From nobody Sat Nov 23 20:04:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 4 Nov 2024 06:43:42 +0000 (GMT) Received: from smtpav06.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E42C25803F; Mon, 4 Nov 2024 06:43:41 +0000 (GMT) Received: from gfwa829.aus.stglabs.ibm.com (unknown [9.3.84.19]) by smtpav06.wdc07v.mail.ibm.com (Postfix) with ESMTP; Mon, 4 Nov 2024 06:43:41 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=ZfhX3YeMVLxQlwGzE sKUbv3aFY83tCbWhOxV2cEhV9Y=; b=cz0CjQYhKWwIMATWOJnEXT9CMCZzEIbW3 oMT5ei3K+Fo4AdofSml66jvldXAI86b1WB97pgTabLeB6rUfUQzWoI8SvbxjfMHu Zz7XxzeCsGcMSxHK8hq839KvpeM8R/qmMTXFtSsIMqMiaeUtjYNIyeJ3PfWC9ND8 E2geadeOa6pyOCM6SPAjEKkeopL8NNjzebab0HT0qPcZ4Gke+sYELv6eTnmMpk1/ UacUJ8YfiMHuKH+9bTCWPmG0GGXJ3oIxX0auGyPxq1mDtNYgw5nTqqHdb4CZZuHe fUtKE1mdXpBPj4iMh1L+ttm4E7w6XIFRlxbAgrsF9ulVHF3XtndaQ== From: dan tan To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, stefanb@linux.vnet.ibm.com, pbonzini@redhat.com, farosas@suse.de, lvivier@redhat.com, clg@kaod.org, dantan@linux.ibm.com Subject: [PATCH v5 2/3] tpm/tpm_tis_spi: activation for the PowerNV machines Date: Mon, 4 Nov 2024 00:43:33 -0600 Message-Id: <20241104064334.21468-3-dantan@linux.vnet.ibm.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241104064334.21468-1-dantan@linux.vnet.ibm.com> References: <20241104064334.21468-1-dantan@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: UpiGm4_f2YoAUQj4DcmPaCJRSskxycvN X-Proofpoint-GUID: UpiGm4_f2YoAUQj4DcmPaCJRSskxycvN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 adultscore=0 spamscore=0 impostorscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 mlxlogscore=823 mlxscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411040057 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=148.163.158.5; envelope-from=dantan@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1730702689798116600 Content-Type: text/plain; charset="utf-8" The addition to ppc/Kconfig is for building this into the qemu-system-ppc64 binary. The enablement requires the following command line argument: -device tpm-tis-spi,tpmdev=3Dtpm0,bus=3Dpnv-spi-bus.4 Signed-off-by: dan tan --- hw/ppc/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index b44d91bebb..56dcf5902e 100644 --- a/hw/ppc/Kconfig +++ b/hw/ppc/Kconfig @@ -39,6 +39,7 @@ config POWERNV select PCI_POWERNV select PCA9552 select PCA9554 + select TPM_TIS_SPI select SERIAL_ISA select SSI select SSI_M25P80 --=20 2.39.5 From nobody Sat Nov 23 20:04:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.vnet.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1730702700; cv=none; d=zohomail.com; s=zohoarc; b=lhkey1O46gqndw0eVtrSniugyFB883i0EfXevsvgE8G794rOrG1YdpCtyHtHlZSEIeLOAFOiqN676TyZJFrJsL93UR7eW9kLcprgJBoy3tyWVxZbYjW4qqJ8sIWobHvFxP4aPgCLY9EOfink1cPYagEPvyn+c+rtPZDRfCcOrSY= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=SCIjfIJbHksVe3DWp N2XNoTD579kqcACg34ZmkwzfSU=; b=n2UEVfmaaFw2S4JtMQWUgCL4nPDrHe1T3 gqcxdk+VKBpdllbIffRvKZFoJwBPXYDrWtrbznQ3xByGAYwcTsjKBqfNdV1P+p1Y x49DJJ3Ka/IEklbkJ0D8x7+4Bsnpgefm8Q1n4XHXLe5lROrioblItJmcm/F8Txzf Y1criqUYHQDjZ1JEYBN6ii+o7vBTRUZgZhJHRtg6nl7g9Sp3wBesgz3iKDvgigZL Pcg90UeFO2ss1r7S+2Fjjm0+QkpEflwnElA1wHAo5rkraK96CABTVDPLpM/cAdv3 t5C/ZQLW+AR4MqQbdiI3XFQP5Ib2+GMsD/jq2jJm9ydIo5fDH9MWw== From: dan tan To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, stefanb@linux.vnet.ibm.com, pbonzini@redhat.com, farosas@suse.de, lvivier@redhat.com, clg@kaod.org, dantan@linux.ibm.com Subject: [PATCH v5 3/3] tests/qtest/tpm: add unit test to tis-spi Date: Mon, 4 Nov 2024 00:43:34 -0600 Message-Id: <20241104064334.21468-4-dantan@linux.vnet.ibm.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241104064334.21468-1-dantan@linux.vnet.ibm.com> References: <20241104064334.21468-1-dantan@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: I0ZQ-S7qVypR8SriIwMfLR7P3-bD-lEO X-Proofpoint-GUID: I0ZQ-S7qVypR8SriIwMfLR7P3-bD-lEO Content-Transfer-Encoding: quoted-printable X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 mlxscore=0 adultscore=0 malwarescore=0 clxscore=1015 spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411040053 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=148.163.158.5; envelope-from=dantan@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1730702702339116600 Content-Type: text/plain; charset="utf-8" Add qtest cases to exercise main TPM functionality The TPM device emulation is provided by swtpm, which is TCG TPM 2.0, and TCG TPM TIS compliant. See https://trustedcomputinggroup.org/wp-content/uploads/TCG_PC_Client_Platform= _TPM_Profile_PTP_2.0_r1.03_v22.pdf https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientTPMInterfa= ceSpecification_TIS__1-3_27_03212013.pdf The SPI registers are specific to the PowerNV platform architecture Signed-off-by: dan tan --- v3: - removed the function prototypes declaration - fixed code format to comply with convention - changed function names and variable names to be the same as the tpm-tis-i2c test. - change hard coded numbers to #define's with meaningful names that are identifiable with spec documentation v4: - git commit amend only v5: - modified tpm_reg_readl() by - removing the special case for TPM_TIS_REG_DID_VID. - however, I did not use the more efficient 32bit access due to the SPI bus master implementation. The 16bit register still require special treatment with the SPI RWX bits. - correcting tpm_reg_readb() with uint16_t reg - tpm_set_verify_loc() added checking for TPM_TIS_CAPABILITIES_SUPPORTED2_0 - test_spi_tpm_transmit_test() added - TPM_TIS_STS_TPM_FAMILY2_0 check in status register - TPM responses verification - fixed the PowerNV stdout msg from running qtest-ppc64/tpm-tis-spi-pnv-test --- tests/qtest/tpm-tis-spi-pnv-test.c | 713 +++++++++++++++++++++++++++++ tests/qtest/meson.build | 2 + 2 files changed, 715 insertions(+) create mode 100644 tests/qtest/tpm-tis-spi-pnv-test.c diff --git a/tests/qtest/tpm-tis-spi-pnv-test.c b/tests/qtest/tpm-tis-spi-p= nv-test.c new file mode 100644 index 0000000000..9eeeea41f7 --- /dev/null +++ b/tests/qtest/tpm-tis-spi-pnv-test.c @@ -0,0 +1,713 @@ +/* + * QTest testcase for a Nuvoton NPCT75x TPM SPI device + * running on the PowerNV machine. + * + * Copyright (c) 2024, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include +#include "libqtest-single.h" +#include "hw/acpi/tpm.h" +#include "hw/pci/pci_ids.h" +#include "qtest_aspeed.h" +#include "tpm-emu.h" +#include "hw/ssi/pnv_spi_regs.h" +#include "pnv-xscom.h" + +#define SPI_TPM_BASE 0xc0080 +#define SPI_SHIFT_COUNTER_N1 0x30000000 +#define SPI_SHIFT_COUNTER_N2 0x40000000 +#define SPI_RWX_OPCODE_SHIFT 56 +#define SPI_RWX_ADDR_SHIFT 32 +#define SPI_CMD_DATA_SHIFT 56 + +#define CFG_COUNT_COMPARE_1 0x0000000200000000 +#define MM_REG_RDR_MATCH 0x00000000ff01ff00 +#define SEQ_OP_REG_BASIC 0x1134416200100000 + +#define TPM_TIS_8BITS_MASK 0xff +#define SPI_TPM_TIS_ADDR 0xd40000 +#define SPI_EXTEND 0x03 +#define TPM_WRITE_OP 0x0 +#define TPM_READ_OP 0x80 + +#define SHORT_MAX_RETRIES 5 +#define LONG_MAX_RETRIES 10 + +static const uint8_t TPM_CMD[12] =3D + "\x80\x01\x00\x00\x00\x0c\x00\x00\x01\x44\x00\x00"; + +#define DPRINTF(fmt, ...) do { \ + if (DEBUG_TIS_TEST) { \ + printf(fmt, ## __VA_ARGS__); \ + } \ +} while (0) + +#define DEBUG_TIS_TEST 0 + +#define DPRINTF_ACCESS \ + DPRINTF("%s: %d: locty=3D%d l=3D%d access=3D0x%02x pending_request_fla= g=3D0x%x\n", \ + __func__, __LINE__, locty, l, access, pending_request_flag) + +#define DPRINTF_STS \ + DPRINTF("%s: %d: sts =3D 0x%08x\n", __func__, __LINE__, sts) + +static uint64_t pnv_spi_tpm_read(const PnvChip *chip, uint32_t reg) +{ + uint32_t pcba =3D SPI_TPM_BASE + reg; + + return qtest_readq(global_qtest, pnv_xscom_addr(chip, pcba)); +} + +static void pnv_spi_tpm_write(const PnvChip *chip, + uint32_t reg, + uint64_t val) +{ + uint32_t pcba =3D SPI_TPM_BASE + reg; + + qtest_writeq(global_qtest, pnv_xscom_addr(chip, pcba), val); +} + +static void spi_op_complete(const PnvChip *chip) +{ + uint64_t cfg_reg; + + cfg_reg =3D pnv_spi_tpm_read(chip, SPI_CLK_CFG_REG); + g_assert_cmpuint(CFG_COUNT_COMPARE_1, =3D=3D, cfg_reg); + pnv_spi_tpm_write(chip, SPI_CLK_CFG_REG, 0); +} + +static void spi_write_reg(const PnvChip *chip, uint64_t val) +{ + int i; + uint64_t spi_sts; + + for (i =3D 0; i < LONG_MAX_RETRIES; i++) { + spi_sts =3D pnv_spi_tpm_read(chip, SPI_STS_REG); + if (GETFIELD(SPI_STS_TDR_FULL, spi_sts) =3D=3D 1) { + sleep(0.5); + } else { + break; + } + } + /* cannot write if SPI_STS_TDR_FULL bit is still set */ + g_assert_cmpuint(0, =3D=3D, GETFIELD(SPI_STS_TDR_FULL, spi_sts)); + pnv_spi_tpm_write(chip, SPI_XMIT_DATA_REG, val); + + for (i =3D 0; i < SHORT_MAX_RETRIES; i++) { + spi_sts =3D pnv_spi_tpm_read(chip, SPI_STS_REG); + if (GETFIELD(SPI_STS_SHIFTER_FSM, spi_sts) & FSM_DONE) { + break; + } else { + sleep(0.1); + } + } + /* it should be done given the amount of time */ + g_assert_cmpuint(0, =3D=3D, GETFIELD(SPI_STS_SHIFTER_FSM, spi_sts) & F= SM_DONE); + spi_op_complete(chip); +} + +static uint64_t spi_read_reg(const PnvChip *chip) +{ + int i; + uint64_t spi_sts, val =3D 0; + + for (i =3D 0; i < LONG_MAX_RETRIES; i++) { + spi_sts =3D pnv_spi_tpm_read(chip, SPI_STS_REG); + if (GETFIELD(SPI_STS_RDR_FULL, spi_sts) =3D=3D 1) { + val =3D pnv_spi_tpm_read(chip, SPI_RCV_DATA_REG); + break; + } + sleep(0.5); + } + for (i =3D 0; i < SHORT_MAX_RETRIES; i++) { + spi_sts =3D pnv_spi_tpm_read(chip, SPI_STS_REG); + if (GETFIELD(SPI_STS_RDR_FULL, spi_sts) =3D=3D 1) { + sleep(0.1); + } else { + break; + } + } + /* SPI_STS_RDR_FULL bit should be reset after read */ + g_assert_cmpuint(0, =3D=3D, GETFIELD(SPI_STS_RDR_FULL, spi_sts)); + spi_op_complete(chip); + return val; +} + +static void spi_access_start(const PnvChip *chip, + bool n2, + uint8_t bytes, + uint8_t tpm_op, + uint32_t tpm_reg) +{ + uint64_t cfg_reg; + uint64_t reg_op; + uint64_t seq_op =3D SEQ_OP_REG_BASIC; + + cfg_reg =3D pnv_spi_tpm_read(chip, SPI_CLK_CFG_REG); + if (cfg_reg !=3D CFG_COUNT_COMPARE_1) { + pnv_spi_tpm_write(chip, SPI_CLK_CFG_REG, CFG_COUNT_COMPARE_1); + } + /* bytes - sequencer operation register bits 24:31 */ + if (n2) { + seq_op |=3D SPI_SHIFT_COUNTER_N2 | (bytes << 0x18); + } else { + seq_op |=3D SPI_SHIFT_COUNTER_N1 | (bytes << 0x18); + } + pnv_spi_tpm_write(chip, SPI_SEQ_OP_REG, seq_op); + pnv_spi_tpm_write(chip, SPI_MM_REG, MM_REG_RDR_MATCH); + pnv_spi_tpm_write(chip, SPI_CTR_CFG_REG, (uint64_t)0); + reg_op =3D ((uint64_t)tpm_op << SPI_RWX_OPCODE_SHIFT) | + ((uint64_t)tpm_reg << SPI_RWX_ADDR_SHIFT); + pnv_spi_tpm_write(chip, SPI_XMIT_DATA_REG, reg_op); +} + +static inline void tpm_reg_writeb(const PnvChip *c, + uint8_t locty, + uint8_t reg, + uint8_t val) +{ + uint32_t tpm_reg_locty =3D SPI_TPM_TIS_ADDR | + (locty << TPM_TIS_LOCALITY_SHIFT); + + spi_access_start(c, false, 1, TPM_WRITE_OP, tpm_reg_locty | reg); + spi_write_reg(c, (uint64_t) val << SPI_CMD_DATA_SHIFT); +} + +static inline uint8_t tpm_reg_readb(const PnvChip *c, + uint8_t locty, + uint16_t reg) +{ + uint32_t tpm_reg_locty =3D SPI_TPM_TIS_ADDR | + (locty << TPM_TIS_LOCALITY_SHIFT); + + spi_access_start(c, true, 1, TPM_READ_OP, tpm_reg_locty | reg); + return spi_read_reg(c); +} + +static inline void tpm_reg_writel(const PnvChip *c, + uint8_t locty, + uint16_t reg, + uint32_t val) +{ + int i; + + for (i =3D 0; i < 4; i++) { + tpm_reg_writeb(c, locty, reg + i, ((val >> (8 * i)) & 0xff)); + } +} + +static inline uint32_t tpm_reg_readl(const PnvChip *c, + uint8_t locty, + uint16_t reg) +{ + uint32_t val =3D 0; + int i; + + for (i =3D 0; i < 4; i++) { + val |=3D tpm_reg_readb(c, locty, reg + i) << (8 * i); + } + return val; +} + +static void tpm_set_verify_loc(const PnvChip *chip, uint8_t loc) +{ + uint8_t access; + uint32_t tpm_sts, capability; + + g_test_message("TPM locality %d tests:", loc); + access =3D tpm_reg_readb(chip, loc, TPM_TIS_REG_ACCESS); + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_STS | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + + capability =3D tpm_reg_readl(chip, loc, TPM_TIS_REG_INTF_CAPABILITY); + g_assert_cmpint(capability, =3D=3D, TPM_TIS_CAPABILITIES_SUPPORTED2_0); + + tpm_reg_writeb(chip, loc, TPM_TIS_REG_ACCESS, TPM_TIS_ACCESS_SEIZE); + tpm_reg_writeb(chip, loc, TPM_TIS_REG_ACCESS, TPM_TIS_ACCESS_REQUEST_U= SE); + + access =3D tpm_reg_readb(chip, loc, TPM_TIS_REG_ACCESS); + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_STS | + TPM_TIS_ACCESS_ACTIVE_LOCALITY | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + g_test_message("\tACCESS REG =3D 0x%x checked", access); + + /* test tpm status register */ + tpm_sts =3D tpm_reg_readl(chip, loc, TPM_TIS_REG_STS); + g_assert_cmpuint((tpm_sts & TPM_TIS_8BITS_MASK), =3D=3D, 0); + g_test_message("\tTPM STATUS: 0x%x, verified", tpm_sts); + + /* release access */ + tpm_reg_writeb(chip, loc, TPM_TIS_REG_ACCESS, + TPM_TIS_ACCESS_ACTIVE_LOCALITY); + access =3D tpm_reg_readb(chip, loc, TPM_TIS_REG_ACCESS); + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_STS | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + g_test_message("\tRELEASED ACCESS: 0x%x, checked", access); +} + +static void test_spi_tpm_locality(const void *data) +{ + const PnvChip *chip =3D &pnv_chips[3]; + uint8_t locality; + + /* Locality 4 has special security restrictions, testing 0-3 */ + for (locality =3D 0; locality < TPM_TIS_NUM_LOCALITIES - 1; locality++= ) { + tpm_set_verify_loc(chip, locality); + } +} + +static void test_spi_tpm_basic(const void *data) +{ + const PnvChip *chip =3D &pnv_chips[3]; + uint32_t didvid, tpm_sts, en_int; + uint8_t access; + + g_test_message("TPM TIS SPI interface basic tests:"); + /* vendor ID and device ID ... check against the known value*/ + didvid =3D tpm_reg_readl(chip, 0, TPM_TIS_REG_DID_VID); + g_assert_cmpint(didvid, =3D=3D, (1 << 16) | PCI_VENDOR_ID_IBM); + g_test_message("\tDID_VID =3D 0x%x, verified", didvid); + + /* access register, default see TCG TIS Spec (v1.3) table-14 */ + access =3D tpm_reg_readb(chip, 0, TPM_TIS_REG_ACCESS); + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_STS | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + g_test_message("\tACCESS REG =3D 0x%x, checked", access); + + /* interrupt enable register, default see TCG TIS Spec (v1.3) table-19= */ + en_int =3D tpm_reg_readl(chip, 0, TPM_TIS_REG_INT_ENABLE); + g_assert_cmpuint(en_int, =3D=3D, TPM_TIS_INT_POLARITY_LOW_LEVEL); + g_test_message("\tINT ENABLE REG: 0x%x, verified", en_int); + + /* status register, default see TCG TIS Spec (v1.3) table-15 */ + tpm_sts =3D tpm_reg_readl(chip, 0, TPM_TIS_REG_STS); + /* for no active locality */ + g_assert_cmpuint(tpm_sts, =3D=3D, 0xffffffff); + g_test_message("\tTPM STATUS: 0x%x, verified", tpm_sts); +} + +/* + * Test case for seizing access by a higher number locality + */ +static void test_spi_tpm_access_seize_test(const void *data) +{ + const PnvChip *chip =3D &pnv_chips[3]; + int locty, l; + uint8_t access; + uint8_t pending_request_flag; + + g_test_message("TPM TIS SPI access seize tests:"); + /* do not test locality 4 (hw only) */ + for (locty =3D 0; locty < TPM_TIS_NUM_LOCALITIES - 1; locty++) { + pending_request_flag =3D 0; + + access =3D tpm_reg_readb(chip, locty, TPM_TIS_REG_ACCESS); + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_STS | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + + /* request use of locality */ + tpm_reg_writeb(chip, locty, TPM_TIS_REG_ACCESS, + TPM_TIS_ACCESS_REQUEST_USE); + + access =3D tpm_reg_readb(chip, locty, TPM_TIS_REG_ACCESS); + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_STS | + TPM_TIS_ACCESS_ACTIVE_LOCALITY | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + + /* lower localities cannot seize access */ + for (l =3D 0; l < locty; l++) { + /* lower locality is not active */ + access =3D tpm_reg_readb(chip, l, TPM_TIS_REG_ACCESS); + DPRINTF_ACCESS; + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_S= TS | + pending_request_flag | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + + /* try to request use from 'l' */ + tpm_reg_writeb(chip, l, TPM_TIS_REG_ACCESS, + TPM_TIS_ACCESS_REQUEST_USE); + + /* + * requesting use from 'l' was not possible; + * we must see REQUEST_USE and possibly PENDING_REQUEST + */ + access =3D tpm_reg_readb(chip, l, TPM_TIS_REG_ACCESS); + DPRINTF_ACCESS; + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_S= TS | + TPM_TIS_ACCESS_REQUEST_USE | + pending_request_flag | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + + /* + * locality 'locty' must be unchanged; + * we must see PENDING_REQUEST + */ + access =3D tpm_reg_readb(chip, locty, TPM_TIS_REG_ACCESS); + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_S= TS | + TPM_TIS_ACCESS_ACTIVE_LOCALITY | + TPM_TIS_ACCESS_PENDING_REQUEST | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + + /* try to seize from 'l' */ + tpm_reg_writeb(chip, l, TPM_TIS_REG_ACCESS, TPM_TIS_ACCESS_SEI= ZE); + /* seize from 'l' was not possible */ + access =3D tpm_reg_readb(chip, l, TPM_TIS_REG_ACCESS); + DPRINTF_ACCESS; + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_S= TS | + TPM_TIS_ACCESS_REQUEST_USE | + pending_request_flag | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + + /* locality 'locty' must be unchanged */ + access =3D tpm_reg_readb(chip, locty, TPM_TIS_REG_ACCESS); + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_S= TS | + TPM_TIS_ACCESS_ACTIVE_LOCALITY | + TPM_TIS_ACCESS_PENDING_REQUEST | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + + /* + * on the next loop we will have a PENDING_REQUEST flag + * set for locality 'l' + */ + pending_request_flag =3D TPM_TIS_ACCESS_PENDING_REQUEST; + } + + /* + * higher localities can 'seize' access but not 'request use'; + * note: this will activate first l+1, then l+2 etc. + */ + for (l =3D locty + 1; l < TPM_TIS_NUM_LOCALITIES - 1; l++) { + /* try to 'request use' from 'l' */ + tpm_reg_writeb(chip, l, TPM_TIS_REG_ACCESS, + TPM_TIS_ACCESS_REQUEST_USE); + + /* + * requesting use from 'l' was not possible; we should see + * REQUEST_USE and may see PENDING_REQUEST + */ + access =3D tpm_reg_readb(chip, l, TPM_TIS_REG_ACCESS); + DPRINTF_ACCESS; + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_S= TS | + TPM_TIS_ACCESS_REQUEST_USE | + pending_request_flag | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + + /* + * locality 'l-1' must be unchanged; we should always + * see PENDING_REQUEST from 'l' requesting access + */ + access =3D tpm_reg_readb(chip, l - 1, TPM_TIS_REG_ACCESS); + DPRINTF_ACCESS; + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_S= TS | + TPM_TIS_ACCESS_ACTIVE_LOCALITY | + TPM_TIS_ACCESS_PENDING_REQUEST | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + + /* try to seize from 'l' */ + tpm_reg_writeb(chip, l, TPM_TIS_REG_ACCESS, TPM_TIS_ACCESS_SEI= ZE); + + /* seize from 'l' was possible */ + access =3D tpm_reg_readb(chip, l, TPM_TIS_REG_ACCESS); + DPRINTF_ACCESS; + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_S= TS | + TPM_TIS_ACCESS_ACTIVE_LOCALITY | + pending_request_flag | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + + /* l - 1 should show that it has BEEN_SEIZED */ + access =3D tpm_reg_readb(chip, l - 1, TPM_TIS_REG_ACCESS); + DPRINTF_ACCESS; + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_S= TS | + TPM_TIS_ACCESS_BEEN_SEIZED | + pending_request_flag | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + + /* clear the BEEN_SEIZED flag and make sure it's gone */ + tpm_reg_writeb(chip, l - 1, TPM_TIS_REG_ACCESS, + TPM_TIS_ACCESS_BEEN_SEIZED); + + access =3D tpm_reg_readb(chip, l - 1, TPM_TIS_REG_ACCESS); + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_S= TS | + pending_request_flag | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + } + + /* + * PENDING_REQUEST will not be set if locty =3D 0 since all locali= ties + * were active; in case of locty =3D 1, locality 0 will be active + * but no PENDING_REQUEST anywhere + */ + if (locty <=3D 1) { + pending_request_flag =3D 0; + } + + /* release access from l - 1; this activates locty - 1 */ + l--; + + access =3D tpm_reg_readb(chip, l, TPM_TIS_REG_ACCESS); + DPRINTF_ACCESS; + + DPRINTF("%s: %d: relinquishing control on l =3D %d\n", + __func__, __LINE__, l); + tpm_reg_writeb(chip, l, TPM_TIS_REG_ACCESS, + TPM_TIS_ACCESS_ACTIVE_LOCALITY); + + access =3D tpm_reg_readb(chip, l, TPM_TIS_REG_ACCESS); + DPRINTF_ACCESS; + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_STS | + pending_request_flag | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + + for (l =3D locty - 1; l >=3D 0; l--) { + access =3D tpm_reg_readb(chip, l, TPM_TIS_REG_ACCESS); + DPRINTF_ACCESS; + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_S= TS | + TPM_TIS_ACCESS_ACTIVE_LOCALITY | + pending_request_flag | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + + /* release this locality */ + tpm_reg_writeb(chip, l, TPM_TIS_REG_ACCESS, + TPM_TIS_ACCESS_ACTIVE_LOCALITY); + + if (l =3D=3D 1) { + pending_request_flag =3D 0; + } + } + + /* no locality may be active now */ + for (l =3D 0; l < TPM_TIS_NUM_LOCALITIES - 1; l++) { + access =3D tpm_reg_readb(chip, l, TPM_TIS_REG_ACCESS); + DPRINTF_ACCESS; + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_S= TS | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + } + g_test_message("\tTPM locality %d seize tests: passed", locty); + } +} + +/* + * Test case for getting access when higher number locality relinquishes a= ccess + */ +static void test_spi_tpm_access_release_test(const void *data) +{ + const PnvChip *chip =3D &pnv_chips[3]; + int locty, l; + uint8_t access; + uint8_t pending_request_flag; + + g_test_message("TPM TIS SPI access release tests:"); + /* do not test locality 4 (hw only) */ + for (locty =3D TPM_TIS_NUM_LOCALITIES - 2; locty >=3D 0; locty--) { + pending_request_flag =3D 0; + + access =3D tpm_reg_readb(chip, locty, TPM_TIS_REG_ACCESS); + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_STS | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + + /* request use of locality */ + tpm_reg_writeb(chip, locty, TPM_TIS_REG_ACCESS, + TPM_TIS_ACCESS_REQUEST_USE); + access =3D tpm_reg_readb(chip, locty, TPM_TIS_REG_ACCESS); + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_STS | + TPM_TIS_ACCESS_ACTIVE_LOCALITY | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + + /* request use of all other localities */ + for (l =3D 0; l < TPM_TIS_NUM_LOCALITIES - 1; l++) { + if (l =3D=3D locty) { + continue; + } + /* + * request use of locality 'l' -- we MUST see REQUEST USE and + * may see PENDING_REQUEST + */ + tpm_reg_writeb(chip, l, TPM_TIS_REG_ACCESS, + TPM_TIS_ACCESS_REQUEST_USE); + access =3D tpm_reg_readb(chip, l, TPM_TIS_REG_ACCESS); + DPRINTF_ACCESS; + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_S= TS | + TPM_TIS_ACCESS_REQUEST_USE | + pending_request_flag | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + pending_request_flag =3D TPM_TIS_ACCESS_PENDING_REQUEST; + } + /* release locality 'locty' */ + tpm_reg_writeb(chip, locty, TPM_TIS_REG_ACCESS, + TPM_TIS_ACCESS_ACTIVE_LOCALITY); + /* + * highest locality should now be active; release it and make sure= the + * next highest locality is active afterwards + */ + for (l =3D TPM_TIS_NUM_LOCALITIES - 2; l >=3D 0; l--) { + if (l =3D=3D locty) { + continue; + } + /* 'l' should be active now */ + access =3D tpm_reg_readb(chip, l, TPM_TIS_REG_ACCESS); + DPRINTF_ACCESS; + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_S= TS | + TPM_TIS_ACCESS_ACTIVE_LOCALITY | + pending_request_flag | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + /* 'l' relinquishes access */ + tpm_reg_writeb(chip, l, TPM_TIS_REG_ACCESS, + TPM_TIS_ACCESS_ACTIVE_LOCALITY); + access =3D tpm_reg_readb(chip, l, TPM_TIS_REG_ACCESS); + DPRINTF_ACCESS; + if (l =3D=3D 1 || (locty <=3D 1 && l =3D=3D 2)) { + pending_request_flag =3D 0; + } + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_S= TS | + pending_request_flag | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + } + g_test_message("\tTPM locality %d seize tests: passed", locty); + } +} + +/* + * Test case for transmitting packets + */ +static void test_spi_tpm_transmit_test(const void *data) +{ + const struct TPMTestState *s =3D data; + const PnvChip *chip =3D &pnv_chips[3]; + uint16_t bcount; + uint8_t access; + uint32_t sts; + int i; + + g_test_message("TPM TIS SPI transmit tests:"); + /* request use of locality 0 */ + tpm_reg_writeb(chip, 0, TPM_TIS_REG_ACCESS, TPM_TIS_ACCESS_REQUEST_USE= ); + access =3D tpm_reg_readb(chip, 0, TPM_TIS_REG_ACCESS); + g_assert_cmpint(access, =3D=3D, TPM_TIS_ACCESS_TPM_REG_VALID_STS | + TPM_TIS_ACCESS_ACTIVE_LOCALITY | + TPM_TIS_ACCESS_TPM_ESTABLISHMENT); + + sts =3D tpm_reg_readl(chip, 0, TPM_TIS_REG_STS); + DPRINTF_STS; + + g_assert_cmpint(sts & 0xff, =3D=3D, 0); + g_assert_cmpint(sts & TPM_TIS_STS_TPM_FAMILY_MASK, =3D=3D, + TPM_TIS_STS_TPM_FAMILY2_0); + + bcount =3D (sts >> 8) & 0xffff; + g_test_message("\t\tbcount: %x, sts: %x", bcount, sts); + g_assert_cmpint(bcount, >=3D, 128); + + tpm_reg_writel(chip, 0, TPM_TIS_REG_STS, TPM_TIS_STS_COMMAND_READY); + sts =3D tpm_reg_readl(chip, 0, TPM_TIS_REG_STS); + DPRINTF_STS; + g_assert_cmpint(sts & 0xff, =3D=3D, TPM_TIS_STS_COMMAND_READY); + + /* transmit command */ + for (i =3D 0; i < sizeof(TPM_CMD); i++) { + tpm_reg_writeb(chip, 0, TPM_TIS_REG_DATA_FIFO, TPM_CMD[i]); + sts =3D tpm_reg_readl(chip, 0, TPM_TIS_REG_STS); + DPRINTF_STS; + if (i < sizeof(TPM_CMD) - 1) { + g_assert_cmpint(sts & 0xff, =3D=3D, TPM_TIS_STS_EXPECT | + TPM_TIS_STS_VALID); + } else { + g_assert_cmpint(sts & 0xff, =3D=3D, TPM_TIS_STS_VALID); + } + /* since STS is read byte-by-byte bcount will be constant 0xff */ + g_assert_cmpint((sts >> 8) & 0xffff, =3D=3D, 0xff); + } + g_test_message("\ttransmit tests, check TPM_TIS_STS_EXPECT"); + + /* start processing */ + tpm_reg_writel(chip, 0, TPM_TIS_REG_STS, TPM_TIS_STS_TPM_GO); + + uint64_t end_time =3D g_get_monotonic_time() + 50 * G_TIME_SPAN_SECOND; + do { + sts =3D tpm_reg_readl(chip, 0, TPM_TIS_REG_STS); + if ((sts & TPM_TIS_STS_DATA_AVAILABLE) !=3D 0) { + break; + } + } while (g_get_monotonic_time() < end_time); + + sts =3D tpm_reg_readl(chip, 0, TPM_TIS_REG_STS); + DPRINTF_STS; + g_assert_cmpint(sts & 0xff, =3D=3D , TPM_TIS_STS_VALID | + TPM_TIS_STS_DATA_AVAILABLE); + /* TCG TIS Spec (v1.3) table-15 */ + g_test_message("\ttransmit tests, check tpmGo (w) & dataAvail (r)"); + bcount =3D (sts >> 8) & 0xffff; + + /* read response */ + uint8_t tpm_msg[sizeof(struct tpm_hdr)]; + g_assert_cmpint(sizeof(tpm_msg), =3D=3D, bcount); + + for (i =3D 0; i < sizeof(tpm_msg); i++) { + tpm_msg[i] =3D tpm_reg_readb(chip, 0, TPM_TIS_REG_DATA_FIFO); + sts =3D tpm_reg_readl(chip, 0, TPM_TIS_REG_STS); + DPRINTF_STS; + if (sts & TPM_TIS_STS_DATA_AVAILABLE) { + g_assert_cmpint((sts >> 8) & 0xffff, =3D=3D, --bcount); + } + } + g_assert_cmpmem(tpm_msg, sizeof(tpm_msg), s->tpm_msg, sizeof(*s->tpm_m= sg)); + + g_test_message("\treceive tests, passed"); + /* relinquish use of locality 0 */ + tpm_reg_writeb(chip, 0, TPM_TIS_REG_ACCESS, TPM_TIS_ACCESS_ACTIVE_LOCA= LITY); + access =3D tpm_reg_readb(chip, 0, TPM_TIS_REG_ACCESS); +} + +int main(int argc, char **argv) +{ + int ret; + char *args; + GThread *thread; + TPMTestState test; + g_autofree char *tmp_path =3D g_dir_make_tmp("qemu-tpm-tis-spi-test.XX= XXXX", + NULL); + + module_call_init(MODULE_INIT_QOM); + g_test_init(&argc, &argv, NULL); + + test.addr =3D g_new0(SocketAddress, 1); + test.addr->type =3D SOCKET_ADDRESS_TYPE_UNIX; + test.addr->u.q_unix.path =3D g_build_filename(tmp_path, "sock", NULL); + g_mutex_init(&test.data_mutex); + g_cond_init(&test.data_cond); + test.data_cond_signal =3D false; + test.tpm_version =3D TPM_VERSION_2_0; + + thread =3D g_thread_new(NULL, tpm_emu_ctrl_thread, &test); + tpm_emu_test_wait_cond(&test); + + args =3D g_strdup_printf("-m 2G -machine powernv10 -smp 2,cores=3D2," + "threads=3D1 -accel tcg,thread=3Dsingle -nographic " + "-serial null -chardev socket,id=3Dchrtpm,path=3D%s " + "-tpmdev emulator,id=3Dtpm0,chardev=3Dchrtpm " + "-device tpm-tis-spi,tpmdev=3Dtpm0,bus=3Dpnv-spi-bus= .4", + test.addr->u.q_unix.path); + qtest_start(args); + qtest_add_data_func("pnv-xscom/tpm-tis-spi/basic_test", + &test, test_spi_tpm_basic); + qtest_add_data_func("pnv-xscom/tpm-tis-spi/locality_test", + &test, test_spi_tpm_locality); + qtest_add_data_func("pnv-xscom/tpm-tis-spi/access_seize_test", + &test, test_spi_tpm_access_seize_test); + qtest_add_data_func("pnv-xscom/tpm-tis-spi/access_release_test", + &test, test_spi_tpm_access_release_test); + qtest_add_data_func("pnv-xscom/tpm-tis-spi/data_transmit_test", + &test, test_spi_tpm_transmit_test); + ret =3D g_test_run(); + + qtest_end(); + g_thread_join(thread); + g_unlink(test.addr->u.q_unix.path); + qapi_free_SocketAddress(test.addr); + g_rmdir(tmp_path); + g_free(args); + return ret; +} + diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index e8be8b3942..74aa9f57e0 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -177,6 +177,7 @@ qtests_ppc64 =3D \ (config_all_devices.has_key('CONFIG_PSERIES') ? ['device-plug-test'] : [= ]) + \ (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-xscom-test'] : [])= + \ (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-spi-seeprom-test']= : []) + \ + (config_all_devices.has_key('CONFIG_POWERNV') ? ['tpm-tis-spi-pnv-test']= : []) + \ (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-host-i2c-test'] : = []) + \ (config_all_devices.has_key('CONFIG_PSERIES') ? ['numa-test'] : []) + = \ (config_all_devices.has_key('CONFIG_PSERIES') ? ['rtas-test'] : []) + = \ @@ -348,6 +349,7 @@ qtests =3D { 'tpm-tis-i2c-test': [io, tpmemu_files, 'qtest_aspeed.c'], 'tpm-tis-device-swtpm-test': [io, tpmemu_files, 'tpm-tis-util.c'], 'tpm-tis-device-test': [io, tpmemu_files, 'tpm-tis-util.c'], + 'tpm-tis-spi-pnv-test': [io, tpmemu_files], 'virtio-net-failover': files('migration-helpers.c'), 'vmgenid-test': files('boot-sector.c', 'acpi-utils.c'), 'netdev-socket': files('netdev-socket.c', '../unit/socket-helpers.c'), --=20 2.39.5