From nobody Sat Nov 23 23:40:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1730702133624986.4448125604449; Sun, 3 Nov 2024 22:35:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7qfu-0003q8-Mu; Mon, 04 Nov 2024 01:34:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7qfs-0003pb-1n for qemu-devel@nongnu.org; Mon, 04 Nov 2024 01:34:52 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7qfp-0007qu-Ia for qemu-devel@nongnu.org; Mon, 04 Nov 2024 01:34:51 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxPOIEayhnP60tAA--.26227S3; Mon, 04 Nov 2024 14:34:44 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMAxjkf8aihn7bY9AA--.50651S3; Mon, 04 Nov 2024 14:34:43 +0800 (CST) From: Bibo Mao To: Song Gao , Paolo Bonzini , Zhao Liu Cc: Jiaxun Yang , Igor Mammedov , Xianglai Li , qemu-devel@nongnu.org Subject: [PATCH v3 1/5] hw/loongarch/virt: Add CPU topology support Date: Mon, 4 Nov 2024 14:34:31 +0800 Message-Id: <20241104063435.4130262-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20241104063435.4130262-1-maobibo@loongson.cn> References: <20241104063435.4130262-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAxjkf8aihn7bY9AA--.50651S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1730702135905116600 Content-Type: text/plain; charset="utf-8" Add topological relationship for Loongarch VCPU and initialize topology member variables, the topo information includes socket-id, core-id and thread-id. For cold-plug CPUs, its topo information is calculated from physical cpuid, and for hot-cpu CPUs its physical cpuid is calculated from topo information. Co-developed-by: Xianglai Li Signed-off-by: Bibo Mao --- docs/system/loongarch/virt.rst | 31 ++++++++++++++++ hw/loongarch/virt.c | 67 ++++++++++++++++++++++++++++------ target/loongarch/cpu.c | 12 ++++++ target/loongarch/cpu.h | 17 +++++++++ 4 files changed, 115 insertions(+), 12 deletions(-) diff --git a/docs/system/loongarch/virt.rst b/docs/system/loongarch/virt.rst index 172fba079e..8daf60785f 100644 --- a/docs/system/loongarch/virt.rst +++ b/docs/system/loongarch/virt.rst @@ -28,6 +28,37 @@ The ``qemu-system-loongarch64`` provides emulation for v= irt machine. You can specify the machine type ``virt`` and cpu type ``la464``. =20 +CPU Topology +------------ + +The ``LA464`` type CPUs have the concept of Socket Core and Thread. + +For example: + +``-smp 1,maxcpus=3DM,sockets=3DS,cores=3DC,threads=3DT`` + +The above parameters indicate that the machine has a maximum of ``M`` vCPU= s and +``S`` sockets, each socket has ``C`` cores, each core has ``T`` threads, +and each thread corresponds to a vCPU. + +Then ``M`` ``S`` ``C`` ``T`` has the following relationship: + +``M =3D S * C * T`` + +In the CPU topology relationship, When we know the ``socket_id`` ``core_id= `` +and ``thread_id`` of the CPU, we can calculate its ``arch_id``: + +``arch_id =3D (socket_id * S) + (core_id * C) + (thread_id * T)`` + +Similarly, when we know the ``arch_id`` of the CPU, +we can also get its ``socket_id`` ``core_id`` and ``thread_id``: + +``socket_id =3D arch_id / (C * T)`` + +``core_id =3D (arch_id / T) % C`` + +``thread_id =3D arch_id % T`` + Boot options ------------ =20 diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 9a635d1d3d..2e4a71bc90 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -1143,7 +1143,6 @@ static void virt_init(MachineState *machine) LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(machine); int i; hwaddr base, size, ram_size =3D machine->ram_size; - const CPUArchIdList *possible_cpus; MachineClass *mc =3D MACHINE_GET_CLASS(machine); CPUState *cpu; =20 @@ -1163,13 +1162,27 @@ static void virt_init(MachineState *machine) memory_region_add_subregion(&lvms->system_iocsr, 0, &lvms->iocsr_mem); =20 /* Init CPUs */ - possible_cpus =3D mc->possible_cpu_arch_ids(machine); - for (i =3D 0; i < possible_cpus->len; i++) { - cpu =3D cpu_create(machine->cpu_type); + mc->possible_cpu_arch_ids(machine); + for (i =3D 0; i < machine->smp.cpus; i++) { + cpu =3D CPU(object_new(machine->cpu_type)); cpu->cpu_index =3D i; machine->possible_cpus->cpus[i].cpu =3D cpu; lacpu =3D LOONGARCH_CPU(cpu); lacpu->phy_id =3D machine->possible_cpus->cpus[i].arch_id; + /* + * The cold-plug CPUs at the time of machine startup will also ent= er + * the CPU hot-plug process when it is created, but at this time, + * the GED device has not been created, resulting in exit in the C= PU + * hot-plug process, which can avoid the incumbent CPU repeatedly + * applying for resources. + * + * The interrupt resource of the in-place CPU will be requested at + * function virt_irq_init(). + * + * The interrupt resource of the subsequently inserted CPU will be + * requested in the CPU hot-plug process. + */ + qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); } fdt_add_cpu_nodes(lvms); fdt_add_memory_nodes(machine); @@ -1286,6 +1299,35 @@ static void virt_initfn(Object *obj) virt_flash_create(lvms); } =20 +static int virt_get_arch_id_from_topo(MachineState *ms, LoongArchCPUTopo *= topo) +{ + int arch_id, sock_vcpu_num, core_vcpu_num; + + /* + * calculate total logical cpus across socket/core/thread. + * For more information on how to calculate the arch_id, + * you can refer to the CPU Topology chapter of the + * docs/system/loongarch/virt.rst document. + */ + sock_vcpu_num =3D topo->socket_id * (ms->smp.threads * ms->smp.cores); + core_vcpu_num =3D topo->core_id * ms->smp.threads; + + /* get vcpu-id(logical cpu index) for this vcpu from this topology */ + arch_id =3D (sock_vcpu_num + core_vcpu_num) + topo->thread_id; + + assert(arch_id >=3D 0 && arch_id < ms->possible_cpus->len); + + return arch_id; +} + +static void virt_get_topo_from_index(MachineState *ms, + LoongArchCPUTopo *topo, int index) +{ + topo->socket_id =3D index / (ms->smp.cores * ms->smp.threads); + topo->core_id =3D index / ms->smp.threads % ms->smp.cores; + topo->thread_id =3D index % ms->smp.threads; +} + static bool memhp_type_supported(DeviceState *dev) { /* we only support pc dimm now */ @@ -1385,8 +1427,9 @@ static HotplugHandler *virt_get_hotplug_handler(Machi= neState *machine, =20 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) { - int n; + int n, arch_id; unsigned int max_cpus =3D ms->smp.max_cpus; + LoongArchCPUTopo topo; =20 if (ms->possible_cpus) { assert(ms->possible_cpus->len =3D=3D max_cpus); @@ -1397,17 +1440,17 @@ static const CPUArchIdList *virt_possible_cpu_arch_= ids(MachineState *ms) sizeof(CPUArchId) * max_cpus); ms->possible_cpus->len =3D max_cpus; for (n =3D 0; n < ms->possible_cpus->len; n++) { + virt_get_topo_from_index(ms, &topo, n); + arch_id =3D virt_get_arch_id_from_topo(ms, &topo); + ms->possible_cpus->cpus[n].vcpus_count =3D 1; ms->possible_cpus->cpus[n].type =3D ms->cpu_type; - ms->possible_cpus->cpus[n].arch_id =3D n; - + ms->possible_cpus->cpus[n].arch_id =3D arch_id; ms->possible_cpus->cpus[n].props.has_socket_id =3D true; - ms->possible_cpus->cpus[n].props.socket_id =3D - n / (ms->smp.cores * ms->smp.threads); + ms->possible_cpus->cpus[n].props.socket_id =3D topo.socket_id; ms->possible_cpus->cpus[n].props.has_core_id =3D true; - ms->possible_cpus->cpus[n].props.core_id =3D - n / ms->smp.threads % ms->smp.cores; + ms->possible_cpus->cpus[n].props.core_id =3D topo.core_id; ms->possible_cpus->cpus[n].props.has_thread_id =3D true; - ms->possible_cpus->cpus[n].props.thread_id =3D n % ms->smp.threads; + ms->possible_cpus->cpus[n].props.thread_id =3D topo.thread_id; } return ms->possible_cpus; } diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 7212fb5f8f..17b65d5946 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -16,6 +16,7 @@ #include "kvm/kvm_loongarch.h" #include "exec/exec-all.h" #include "cpu.h" +#include "hw/qdev-properties.h" #include "internals.h" #include "fpu/softfloat-helpers.h" #include "cpu-csr.h" @@ -682,6 +683,7 @@ static void loongarch_cpu_init(Object *obj) timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL, &loongarch_constant_timer_cb, cpu); #endif + cpu->phy_id =3D UNSET_PHY_ID; #endif } =20 @@ -780,6 +782,14 @@ static int64_t loongarch_cpu_get_arch_id(CPUState *cs) } #endif =20 +static Property loongarch_cpu_properties[] =3D { + DEFINE_PROP_INT32("socket-id", LoongArchCPU, socket_id, 0), + DEFINE_PROP_INT32("core-id", LoongArchCPU, core_id, 0), + DEFINE_PROP_INT32("thread-id", LoongArchCPU, thread_id, 0), + DEFINE_PROP_INT32("node-id", LoongArchCPU, node_id, CPU_UNSET_NUMA_NOD= E_ID), + DEFINE_PROP_END_OF_LIST() +}; + static void loongarch_cpu_class_init(ObjectClass *c, void *data) { LoongArchCPUClass *lacc =3D LOONGARCH_CPU_CLASS(c); @@ -787,6 +797,7 @@ static void loongarch_cpu_class_init(ObjectClass *c, vo= id *data) DeviceClass *dc =3D DEVICE_CLASS(c); ResettableClass *rc =3D RESETTABLE_CLASS(c); =20 + device_class_set_props(dc, loongarch_cpu_properties); device_class_set_parent_realize(dc, loongarch_cpu_realizefn, &lacc->parent_realize); resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold,= NULL, @@ -811,6 +822,7 @@ static void loongarch_cpu_class_init(ObjectClass *c, vo= id *data) #ifdef CONFIG_TCG cc->tcg_ops =3D &loongarch_tcg_ops; #endif + dc->user_creatable =3D true; } =20 static const gchar *loongarch32_gdb_arch_name(CPUState *cs) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 6c41fafb70..fb50cbbeee 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -19,6 +19,12 @@ #include "cpu-csr.h" #include "cpu-qom.h" =20 +/* + * CPU can't have 0xFFFFFFFF physical ID, use that value to distinguish + * that physical ID hasn't been set yet + */ +#define UNSET_PHY_ID 0xFFFFFFFF + #define IOCSRF_TEMP 0 #define IOCSRF_NODECNT 1 #define IOCSRF_MSI 2 @@ -369,6 +375,12 @@ typedef struct CPUArchState { #endif } CPULoongArchState; =20 +typedef struct LoongArchCPUTopo { + int32_t socket_id; /* socket-id of this VCPU */ + int32_t core_id; /* core-id of this VCPU */ + int32_t thread_id; /* thread-id of this VCPU */ +} LoongArchCPUTopo; + /** * LoongArchCPU: * @env: #CPULoongArchState @@ -381,6 +393,10 @@ struct ArchCPU { CPULoongArchState env; QEMUTimer timer; uint32_t phy_id; + int32_t socket_id; /* socket-id of this VCPU */ + int32_t core_id; /* core-id of this VCPU */ + int32_t thread_id; /* thread-id of this VCPU */ + int32_t node_id; /* NUMA node of this VCPU */ =20 /* 'compatible' string for this CPU for Linux device trees */ const char *dtb_compatible; @@ -399,6 +415,7 @@ struct LoongArchCPUClass { CPUClass parent_class; =20 DeviceRealize parent_realize; + DeviceUnrealize parent_unrealize; ResettablePhases parent_phases; }; =20 --=20 2.39.3