From nobody Sat Nov 23 20:34:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1730690557; cv=none; d=zohomail.com; s=zohoarc; b=JtKzLBZsLltJlHZtS4NLQv+oUfBY32yBforiXgIrFr5/TlnkYnhh3QY/AyNZmfRnBU2KLu0T8XpV6nzjrSUSH1WlO9HdCX/3+FaVJMxJBCFvojcrWTj1Vt+L/aK5pD1G8zEia1krtNtnx5PXuCKj+F1YOf5wbIWpNmiLf8KK7Q0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730690557; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=NRvwOS2K0fG6X6uEaaDIDd1n5VvoY51iyHU3hSFoGYM=; b=kA0+NC/WJRpvXq8pK6BlARTTrYMSgxGVIgO/eAPvuHjoNVLX4glqdlCRnfWBODN6am/ZZTBTy/q+d/qc3eWY87dG5/jhvBtKnIexvQ7jAg+qgwbvw23jj2SWnWt7Z6GeQTXXftJF3UdB045TqOJvr/nws1xhb45thw++2M3rjHY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1730690557236596.3696617096878; Sun, 3 Nov 2024 19:22:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7nei-0005uC-W8; Sun, 03 Nov 2024 22:21:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7neX-0005rm-Mz; Sun, 03 Nov 2024 22:21:18 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7neV-0004QT-UF; Sun, 03 Nov 2024 22:21:17 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 4 Nov 2024 11:21:05 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 4 Nov 2024 11:21:05 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:SD (Secure Card)" CC: , , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v2 1/3] hw/sd/sdhci: Fix coding style Date: Mon, 4 Nov 2024 11:21:02 +0800 Message-ID: <20241104032104.2784183-2-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241104032104.2784183-1-jamin_lin@aspeedtech.com> References: <20241104032104.2784183-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1730690558715116600 Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/sd/sdhci.c | 64 +++++++++++++++++++++++++++++++++------------------ 1 file changed, 42 insertions(+), 22 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index ed01499391..db7d547156 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -234,7 +234,7 @@ static void sdhci_raise_insertion_irq(void *opaque) =20 if (s->norintsts & SDHC_NIS_REMOVE) { timer_mod(s->insert_timer, - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERT= ION_DELAY); + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DEL= AY); } else { s->prnsts =3D 0x1ff0000; if (s->norintstsen & SDHC_NISEN_INSERT) { @@ -252,7 +252,7 @@ static void sdhci_set_inserted(DeviceState *dev, bool l= evel) if ((s->norintsts & SDHC_NIS_REMOVE) && level) { /* Give target some time to notice card ejection */ timer_mod(s->insert_timer, - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERT= ION_DELAY); + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DEL= AY); } else { if (level) { s->prnsts =3D 0x1ff0000; @@ -290,9 +290,11 @@ static void sdhci_reset(SDHCIState *s) timer_del(s->insert_timer); timer_del(s->transfer_timer); =20 - /* Set all registers to 0. Capabilities/Version registers are not clea= red + /* + * Set all registers to 0. Capabilities/Version registers are not clea= red * and assumed to always preserve their value, given to them during - * initialization */ + * initialization + */ memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmas= ysad); =20 /* Reset other state based on current card insertion/readonly status */ @@ -306,7 +308,8 @@ static void sdhci_reset(SDHCIState *s) =20 static void sdhci_poweron_reset(DeviceState *dev) { - /* QOM (ie power-on) reset. This is identical to reset + /* + * QOM (ie power-on) reset. This is identical to reset * commanded via device register apart from handling of the * 'pending insert on powerup' quirk. */ @@ -446,8 +449,10 @@ static void sdhci_read_block_from_card(SDHCIState *s) s->prnsts &=3D ~SDHC_DAT_LINE_ACTIVE; } =20 - /* If stop at block gap request was set and it's not the last block of - * data - generate Block Event interrupt */ + /* + * If stop at block gap request was set and it's not the last block of + * data - generate Block Event interrupt + */ if (s->stopped_state =3D=3D sdhc_gap_read && (s->trnmod & SDHC_TRNS_MU= LTI) && s->blkcnt !=3D 1) { s->prnsts &=3D ~SDHC_DAT_LINE_ACTIVE; @@ -549,8 +554,10 @@ static void sdhci_write_block_to_card(SDHCIState *s) sdhci_update_irq(s); } =20 -/* Write @size bytes of @value data to host controller @s Buffer Data Port - * register */ +/* + * Write @size bytes of @value data to host controller @s Buffer Data Port + * register + */ static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned s= ize) { unsigned i; @@ -595,9 +602,11 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIStat= e *s) return; } =20 - /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account f= or + /* + * XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account f= or * possible stop at page boundary if initial address is not page align= ed, - * allow them to work properly */ + * allow them to work properly + */ if ((s->sdmasysad % boundary_chk) =3D=3D 0) { page_aligned =3D true; } @@ -703,7 +712,8 @@ static void get_adma_description(SDHCIState *s, ADMADes= cr *dscr) dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2), MEMTXATTRS_UNSPECIFIED); adma2 =3D le64_to_cpu(adma2); - /* The spec does not specify endianness of descriptor table. + /* + * The spec does not specify endianness of descriptor table. * We currently assume that it is LE. */ dscr->addr =3D (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; @@ -978,8 +988,10 @@ static bool sdhci_can_issue_command(SDHCIState *s) return true; } =20 -/* The Buffer Data Port register must be accessed in sequential and - * continuous manner */ +/* + * The Buffer Data Port register must be accessed in sequential and + * continuous manner + */ static inline bool sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) { @@ -1207,8 +1219,10 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t va= l, unsigned size) MASKED_WRITE(s->argument, mask, value); break; case SDHC_TRNMOD: - /* DMA can be enabled only if it is supported as indicated by - * capabilities register */ + /* + * DMA can be enabled only if it is supported as indicated by + * capabilities register + */ if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { value &=3D ~SDHC_TRNS_DMA; } @@ -1280,8 +1294,10 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t va= l, unsigned size) } else { s->norintsts &=3D ~SDHC_NIS_ERR; } - /* Quirk for Raspberry Pi: pending card insert interrupt - * appears when first enabled after power on */ + /* + * Quirk for Raspberry Pi: pending card insert interrupt + * appears when first enabled after power on + */ if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_stat= e) { assert(s->pending_insert_quirk); s->norintsts |=3D SDHC_NIS_INSERT; @@ -1397,8 +1413,10 @@ void sdhci_initfn(SDHCIState *s) { qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SDHCI_BUS, DEVICE(s), "sd-= bus"); =20 - s->insert_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_inser= tion_irq, s); - s->transfer_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_tran= sfer, s); + s->insert_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + sdhci_raise_insertion_irq, s); + s->transfer_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + sdhci_data_transfer, s); =20 s->io_ops =3D &sdhci_mmio_le_ops; } @@ -1446,11 +1464,13 @@ void sdhci_common_realize(SDHCIState *s, Error **er= rp) =20 void sdhci_common_unrealize(SDHCIState *s) { - /* This function is expected to be called only once for each class: + /* + * This function is expected to be called only once for each class: * - SysBus: via DeviceClass->unrealize(), * - PCI: via PCIDeviceClass->exit(). * However to avoid double-free and/or use-after-free we still nullify - * this variable (better safe than sorry!). */ + * this variable (better safe than sorry!). + */ g_free(s->fifo_buffer); s->fifo_buffer =3D NULL; } --=20 2.34.1 From nobody Sat Nov 23 20:34:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1730690545; cv=none; d=zohomail.com; s=zohoarc; b=UEquAXAZb0LLS5lSu+tfFY/9fQ/8GMv0UK4jA5qXWwCFDfSrKg1vH28X8JRUQoNSshdnRto/hK4ZgSkXX/QHx0nYe522P4rGPYSEu9iWniIs3a/N57uHjJ4shmkfh6KoWg7DhjiPzDr2T5BK75TlK2lnxHOcHz4gjzrTOhMe7qk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730690545; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=e0zJcZRcqg+1NOKgVvtGJzI5LhPoSpDJ/Aj0JjaDGoc=; b=FacDvTYIvIunW96q43y3cTkDJqVBCYA2kWhZ08O2dV1yZ20onuQSRIc8/8nBeWIDegN1+XEbgMwYZYYbI1kfl9XBc0ettr957x7G3jD0Z7xqiU0XQIb7MLlUFagjhMfM0ZleH7BiFryl528rbUM5SezljsLdslIo+F52oJyRbb4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1730690545093438.9136175877153; Sun, 3 Nov 2024 19:22:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7nej-0005uG-NM; Sun, 03 Nov 2024 22:21:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7nea-0005sH-E7; Sun, 03 Nov 2024 22:21:21 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7neZ-0004QT-1g; Sun, 03 Nov 2024 22:21:20 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 4 Nov 2024 11:21:05 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 4 Nov 2024 11:21:05 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:SD (Secure Card)" CC: , , Subject: [PATCH v2 2/3] hw/sd/sdhci: Introduce a new Write Protected pin inverted property Date: Mon, 4 Nov 2024 11:21:03 +0800 Message-ID: <20241104032104.2784183-3-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241104032104.2784183-1-jamin_lin@aspeedtech.com> References: <20241104032104.2784183-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1730690547975116600 Content-Type: text/plain; charset="utf-8" The Write Protect pin of SDHCI model is default active low to match the SDH= CI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). However, some boards are design Write Protected pin active high. In other words, write enable the bi= t 19 should be 0 and write protected the bit 19 should be 1 at the Present State Register (0x24). To support it, introduces a new "wp-inverted" property and set it false by default. Signed-off-by: Jamin Lin Acked-by: C=C3=A9dric Le Goater --- hw/sd/sdhci.c | 6 ++++++ include/hw/sd/sdhci.h | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index db7d547156..c675543873 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -275,6 +275,10 @@ static void sdhci_set_readonly(DeviceState *dev, bool = level) { SDHCIState *s =3D (SDHCIState *)dev; =20 + if (s->wp_inverted) { + level =3D !level; + } + if (level) { s->prnsts &=3D ~SDHC_WRITE_PROTECT; } else { @@ -1551,6 +1555,8 @@ static Property sdhci_sysbus_properties[] =3D { false), DEFINE_PROP_LINK("dma", SDHCIState, dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_BOOL("wp-inverted", SDHCIState, + wp_inverted, false), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 6cd2822f1d..25ad9ed778 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -100,6 +100,11 @@ struct SDHCIState { uint8_t sd_spec_version; uint8_t uhs_mode; uint8_t vendor; /* For vendor specific functionality */ + /* + * Write Protect pin default active low for detecting SD card + * to be protected. Set wp_inverted to true inverted the signal. + */ + bool wp_inverted; }; typedef struct SDHCIState SDHCIState; =20 --=20 2.34.1 From nobody Sat Nov 23 20:34:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1730690498; cv=none; d=zohomail.com; s=zohoarc; b=nnQcyDwjfFFK2+R/sTgJGn5l/QWPTfMHmki70ApeouRZLbDjgtWYLvg+DaZ23DxXmNi36Fc4c/jpH5WXscLa2IcUn1ZRZmH3ecGwC8x9cS+Bt8tMcKeF5W2Tujkt+djtxnAgYcadWlQSL9AB+9tCqMAkTS4PJ9a3Z1SZw8/M4xU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730690498; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=512/x28u82VXcEnSSDsIYLsd2y17bA9qyMMdWYd//BQ=; b=mJ4X8xjdG8pAR1T7GEk8fqqvmNDXJ2fVEkTrpjzQaFNb/Bf0xI506hmK0oyuUMm85kRnuZgeGj9FgTZWM8AHgC8xEOsX6T6K/AQ6HWcD6mTd3YsyrtRRv8TtX6pTacaVyxsOA0FjSje1zvKdU7ahfH0OPxeCUFZrvVezy0hhI+E= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 173069049842787.9739451219773; Sun, 3 Nov 2024 19:21:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7nel-0005uo-4J; Sun, 03 Nov 2024 22:21:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7nec-0005sa-ST; Sun, 03 Nov 2024 22:21:26 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7neb-0004QT-GQ; Sun, 03 Nov 2024 22:21:22 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 4 Nov 2024 11:21:05 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 4 Nov 2024 11:21:05 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:SD (Secure Card)" CC: , , Subject: [PATCH v2 3/3] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 and AST2500 EVBs Date: Mon, 4 Nov 2024 11:21:04 +0800 Message-ID: <20241104032104.2784183-4-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241104032104.2784183-1-jamin_lin@aspeedtech.com> References: <20241104032104.2784183-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1730690501526116600 Content-Type: text/plain; charset="utf-8" The Write Protect pin of SDHCI model is default active low to match the SDH= CI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). According to the design of AST2500 and AST2600 EVBs, the Write Protected pin is active high by default. To support it, introduces a new "sdhci_wp_invert= ed" property in ASPEED MACHINE State and set it true for AST2500 and AST2600 EV= Bs and set "wp_inverted" property true of sdhci-generic model. Signed-off-by: Jamin Lin Reviewed-by: Andrew Jeffery --- hw/arm/aspeed.c | 8 ++++++++ include/hw/arm/aspeed.h | 1 + 2 files changed, 9 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index e447923536..b10033d536 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -403,6 +403,12 @@ static void aspeed_machine_init(MachineState *machine) OBJECT(get_system_memory()), &error_abort); object_property_set_link(OBJECT(bmc->soc), "dram", OBJECT(machine->ram), &error_abort); + if (amc->sdhci_wp_inverted) { + for (i =3D 0; i < bmc->soc->sdhci.num_slots; i++) { + object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]), + "wp-inverted", true, &error_abort); + } + } if (machine->kernel_filename) { /* * When booting with a -kernel command line there is no u-boot @@ -1308,6 +1314,7 @@ static void aspeed_machine_ast2500_evb_class_init(Obj= ectClass *oc, void *data) amc->fmc_model =3D "mx25l25635e"; amc->spi_model =3D "mx25l25635f"; amc->num_cs =3D 1; + amc->sdhci_wp_inverted =3D true; amc->i2c_init =3D ast2500_evb_i2c_init; mc->default_ram_size =3D 512 * MiB; aspeed_machine_class_init_cpus_defaults(mc); @@ -1409,6 +1416,7 @@ static void aspeed_machine_ast2600_evb_class_init(Obj= ectClass *oc, void *data) amc->num_cs =3D 1; amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON; + amc->sdhci_wp_inverted =3D true; amc->i2c_init =3D ast2600_evb_i2c_init; mc->default_ram_size =3D 1 * GiB; aspeed_machine_class_init_cpus_defaults(mc); diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index cbeacb214c..9cae45a1c9 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -39,6 +39,7 @@ struct AspeedMachineClass { uint32_t macs_mask; void (*i2c_init)(AspeedMachineState *bmc); uint32_t uart_default; + bool sdhci_wp_inverted; }; =20 =20 --=20 2.34.1