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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.22.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:22:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679745; x=1731284545; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uJHQWHKZNwdpX5xpE4NGKUgAt0/AlwETGxPvV8xdFsM=; b=WUVVc0GUPXctFFWoLOGOVIwCRA9CiHiCNrzlVHmp1EFF97W9SjkG+8ywjpbMmmu5p3 GAMM8CHHMW4cJmpkdQCTlOjm4VUyHZyIJLZI+7FDLMgBBbRW8w56zlazgwFhouoxRVi4 28OD3Fe4sQqYz35bjpg3qQqJx+AR6YBch5V/zY2dNAN5ObcC+phAZLuhCs0mCdkYtlMb 9OuUS1hCXdvb6aLSSMgHRL8ZzvidBzohCnGS6C0bQKOcyi/fJAvLiT1tBr39X//sCzlQ fshFOdlX/Y9FhHArYE1UyqBBgTt3MDv1xf+rIah7t2xwt3Ger4BCtAIAM7mVXnL3Vmnj 3vOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679745; x=1731284545; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uJHQWHKZNwdpX5xpE4NGKUgAt0/AlwETGxPvV8xdFsM=; b=F4zQ1UjinPuiR8CBJ+G2MZxTekSzsmbF6LaNOgiXX2sfOtWZhy9+Mp89o838NM7Kxe XDeaUHTWTTcl5Qju6kZ8blfS0Im6RPDWoQ07GCy2Tx6hXkxxmTJt2SWBU9H6gs5b5wWv 1aRLZE7Bj8ibYscrJ7Fs+kszJ2M4bI1zdGKz/2whaQ4W2BUT8eESdT+fA0c2HDfV0/t3 cKO+5H5XJenUXZY1k8lbAnlxUJ8X55xqUd/aSEwKuYz+52Gyq+9UJRBycQ+ZtzIM/BRF Vavip25feQWP2I1NbDd2i4oPyVQgh6Pmwszc7nuEQZF/XJNFKpp2E0t9MT7AxqNEN/wK JWYQ== X-Forwarded-Encrypted: i=1; AJvYcCVM5sxTgHY+FIdr7PpxrC3AqHIe7xCiB/GumARvl+o9GVZryEBV/5ZL2Lz7iBS3hZ8If3yPNyAeQg==@nongnu.org X-Gm-Message-State: AOJu0YycjS3eODlPDPVsujW9N/9P9keTiKBA9GFvlf9R9gJDYvowgfDR lPIsnxldn6y4iIXmflt4ZByGIZsn6x0KEWMfxj2FadfH3QypZMH/FI86Sw== X-Google-Smtp-Source: AGHT+IEQT+RFtjXPGWFUghrD43LUNWG56ge+40NlYqaG9LpsZjeSCaiTAvG/KMAflDbSsNlc+hdu2A== X-Received: by 2002:a05:6300:4043:b0:1d9:2bed:c7e8 with SMTP id adf61e73a8af0-1dba55aaf69mr20671540637.35.1730679744964; Sun, 03 Nov 2024 16:22:24 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Glenn Miles , Michael Kowal , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 54/67] ppc/xive2: Allow 1-byte write of Target field in TIMA Date: Mon, 4 Nov 2024 10:18:43 +1000 Message-ID: <20241104001900.682660-55-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=npiggin@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1730679964118116600 From: Glenn Miles When running PowerVM, the console is littered with XIVE traces regarding invalid writes to TIMA address 0x100b6 due to a lack of support for writes to the "TARGET" field which was added for XIVE GEN2. To fix this, we add special op support for 1-byte writes to this field. Signed-off-by: Glenn Miles Signed-off-by: Michael Kowal Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Nicholas Piggin --- hw/intc/xive.c | 2 ++ hw/intc/xive2.c | 13 +++++++++++++ include/hw/ppc/xive2.h | 2 ++ include/hw/ppc/xive_regs.h | 1 + 4 files changed, 18 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index caa8dc74b6..574ac685c3 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -546,6 +546,8 @@ static const XiveTmOp xive2_tm_operations[] =3D { NULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_T, 1, xive2_tm_set_hv_targe= t, + NULL }, =20 /* MMIOs above 2K : special operations with side effects */ { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 26b6e72129..8d3d69a0db 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -585,6 +585,19 @@ void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCT= X *tctx, } } =20 +static void xive2_tctx_set_target(XiveTCTX *tctx, uint8_t ring, uint8_t ta= rget) +{ + uint8_t *regs =3D &tctx->regs[ring]; + + regs[TM_T] =3D target; +} + +void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size) +{ + xive2_tctx_set_target(tctx, TM_QW3_HV_PHYS, value & 0xff); +} + /* * XIVE Router (aka. Virtualization Controller or IVRE) */ diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h index b7a7c33ddd..36bd0e747f 100644 --- a/include/hw/ppc/xive2.h +++ b/include/hw/ppc/xive2.h @@ -121,5 +121,7 @@ uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, Xive= TCTX *tctx, hwaddr offset, unsigned size); void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size); +void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size); =20 #endif /* PPC_XIVE2_H */ diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 27a744d50d..f8f05deafd 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -79,6 +79,7 @@ #define TM_INC 0x5 /* - + - + */ #define TM_LGS 0x5 /* + + + + */ /* Rename P10 */ #define TM_AGE 0x6 /* - + - + */ +#define TM_T 0x6 /* - + - + */ /* Rename P10 */ #define TM_PIPR 0x7 /* - + - + */ #define TM_OGEN 0xF /* - + - - */ /* P10 only */ =20 --=20 2.45.2