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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.19.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:19:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679563; x=1731284363; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZqpqSjhDlR0KKOwKpuJzD0Sk7j1XMBWO2P6fYwp7tiY=; b=Be+oU7wYANy+A7XdBjU1USzy4P/GOUk8yaUqpcYcntE8TvpelzHAB3qdGzWUCWxyt8 v3sGMP8Oda3XOVcu7iXXURQJUY46LP/ZsGZAx4sZtuPdGkR/Gib4MjjVywW31Xl9yrat EFbRXEceDhkhfXBZY+XbAg0rw6KGE22sHWTNRra38bibzxmWepw49ISSatAtEZeQVh91 3l5xMkwTmU9L5wkJwcpKUEtl2eM2INtVsv1AnprBfkZizL2dct9QlRO+t0TjZrCPKJBu GkEKHl/WntCqxmV76nHAyuwY+WVnMP4VFjjNe81aVzToA6VhwTiZiht2oN+lgGC8Imux dDkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679563; x=1731284363; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZqpqSjhDlR0KKOwKpuJzD0Sk7j1XMBWO2P6fYwp7tiY=; b=HK26RYsIrU5Hcl600NEY6+sXcsF4dht2Uce28ZAhgNUSBC/Qc9U22X77DyURbntn+d ni4p0N/hGK8IredOx/jHbONkXvSie2cOXTjSgIfA7IsEfYmo94+pdLQgrVei68RgZLUB Nx6f5n0MUOBlI67RYehBFNs8/ovhJfK4CL+AdnltbPzJwxhRoQ9a6+aeDyBfUvxqPBzl oEHSyZs2qUeT1H2/9Cv+5Xd+O9zQlRDylmswGUNSeVDSLpl0A3NkBjD0euLNZYlZdlkL ZRs2bNhDBiLrYHbWJrAoDO6jnZvUOIiSIINzOGRQTH/15/YqlKsijRG3cEnONF5N2AOc sApA== X-Forwarded-Encrypted: i=1; AJvYcCUiGKKrPHcpy0MCMEP+NRBYLMCNOhKmKmM5erleow/f56ADWL/QK17yo2Y4hUOANjuiS1o2w+6ycQRMfWQ=@nongnu.org, AJvYcCX97hg8vSthGqKq+fOjkx3dld8GKiJtRkF23qoFBUWeSI0FmBMkS+mnwxhDUHps8RV9JEsHonxBQQ==@nongnu.org X-Gm-Message-State: AOJu0Yw5JVDa18yy1lBnP1w8940aoh7R0jR2Qz75nLWdVuw/Kxlphbbe U+sOkycYrSdGSCe7hDj6FqRbqXkJidUwGkXy8nOgI+5JgyejFUFjohsJtg== X-Google-Smtp-Source: AGHT+IGcGQYzgmsuMRDc2LVhOvirDpy9UtjXc4h4NdNmHRzW7i4XpkwRLUyJEqVzTLIp7n8398y6RQ== X-Received: by 2002:a05:6a20:d493:b0:1d9:111f:4b46 with SMTP id adf61e73a8af0-1db91d86c41mr20656991637.12.1730679563177; Sun, 03 Nov 2024 16:19:23 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, qemu-stable@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Richard Henderson Subject: [PULL 03/67] ppc/pnv: Fix LPC serirq routing calculation Date: Mon, 4 Nov 2024 10:17:52 +1000 Message-ID: <20241104001900.682660-4-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=npiggin@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1730679656954116600 The serirq routing table is split over two registers, the calculation for the high irqs in the second register did not subtract the irq offset. This was spotted by Coverity as a shift-by-negative. Fix this and change the open-coded shifting and masking to use extract32() function so it's less error-prone. This went unnoticed because irqs >=3D 14 are not used in a standard QEMU/OPAL boot, changing the first QEMU serial-isa irq to 14 to test does demonstrate serial irqs aren't received, and that this change fixes that. Cc: qemu-stable@nongnu.org Reported-by: C=C3=A9dric Le Goater Resolves: Coverity CID 1558829 (partially) Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Richard Henderson Signed-off-by: Nicholas Piggin --- hw/ppc/pnv_lpc.c | 10 ++++++++-- target/ppc/cpu.h | 1 + 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index f8aad955b5..80b79dfbbc 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -435,13 +435,19 @@ static void pnv_lpc_eval_serirq_routes(PnvLpcControll= er *lpc) return; } =20 + /* + * Each of the ISA irqs is routed to one of the 4 SERIRQ irqs with 2 + * bits, split across 2 OPB registers. + */ for (irq =3D 0; irq <=3D 13; irq++) { - int serirq =3D (lpc->opb_irq_route1 >> (31 - 5 - (irq * 2))) & 0x3; + int serirq =3D extract32(lpc->opb_irq_route1, + PPC_BIT32_NR(5 + irq * 2), 2); lpc->irq_to_serirq_route[irq] =3D serirq; } =20 for (irq =3D 14; irq < ISA_NUM_IRQS; irq++) { - int serirq =3D (lpc->opb_irq_route0 >> (31 - 9 - (irq * 2))) & 0x3; + int serirq =3D extract32(lpc->opb_irq_route0, + PPC_BIT32_NR(9 + (irq - 14) * 2), 2); lpc->irq_to_serirq_route[irq] =3D serirq; } } diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 321ed2da75..bd32a1a5f8 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -40,6 +40,7 @@ =20 #define PPC_BIT_NR(bit) (63 - (bit)) #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) +#define PPC_BIT32_NR(bit) (31 - (bit)) #define PPC_BIT32(bit) (0x80000000 >> (bit)) #define PPC_BIT8(bit) (0x80 >> (bit)) #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) --=20 2.45.2