From nobody Sat Nov 23 23:30:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1730629637; cv=none; d=zohomail.com; s=zohoarc; b=mG3adGdSdHPtsq8ugLXjmMJfRqeoS+FvUBvA/C4gLtldpSz8TNiY/aEMyzj7ezbug403LSdnO/duy2uqn5icn3QJ1bVzPYB2P4rK4GvoLpCt6erMZ+MmLVqUJjEnus1pp39Q2qwKINEJbjWw+x/1c8fc7kOoDLM1DyWdqj93svI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730629637; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=8zpqM/68KZ0Fg+/60BTKVnxsfGmTRgyqzwp6RwzYobM=; b=XfZyLNuxUWFi9HGLY0OU2g2B5TmONmnqItj7aAEAKoqvNwYFXR0lqF8qKo3w93kFa70tVcNGHJU0NI2kpMGNkCqp7XAh63gU+D2N0P/vuhwutok0uC7O6hFnB8hg1y9xUbNvKHaiExKFfTWcrhT0eSlUFMQjBsNWb8vR9BVsl8Y= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1730629637465852.7952185613883; Sun, 3 Nov 2024 02:27:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7XoU-00073e-TC; Sun, 03 Nov 2024 05:26:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7XoS-00072v-Vf; Sun, 03 Nov 2024 05:26:28 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7XoR-0005lz-0V; Sun, 03 Nov 2024 05:26:28 -0500 Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4Xh9g64K68z6K5p5; Sun, 3 Nov 2024 18:23:46 +0800 (CST) Received: from frapeml500007.china.huawei.com (unknown [7.182.85.172]) by mail.maildlp.com (Postfix) with ESMTPS id E37F1140451; Sun, 3 Nov 2024 18:26:23 +0800 (CST) Received: from 00293818-MRGF.huawei.com (10.48.154.43) by frapeml500007.china.huawei.com (7.182.85.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Sun, 3 Nov 2024 11:26:04 +0100 To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH V3 3/5] hw/acpi: Update ACPI `_STA` method with QOM vCPU ACPI Hotplug states Date: Sun, 3 Nov 2024 10:24:17 +0000 Message-ID: <20241103102419.202225-4-salil.mehta@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241103102419.202225-1-salil.mehta@huawei.com> References: <20241103102419.202225-1-salil.mehta@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.48.154.43] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To frapeml500007.china.huawei.com (7.182.85.172) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta From: Salil Mehta via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1730629639242116600 Content-Type: text/plain; charset="utf-8" Reflect the QOM vCPUs ACPI CPU hotplug states in the `_STA.Present` and and `_STA.Enabled` bits when the guest kernel evaluates the ACPI `_STA` method during initialization, as well as when vCPUs are hot-plugged or hot-unplugged. If the CPU is present then the its `enabled` status can be fetched using architecture-specific code [1]. Reference: [1] Example implementation of architecture-specific hook to fetch CPU `enabled status Link: https://github.com/salil-mehta/qemu/commit/c0b416b11e5af6505e5588= 66f0eb6c9f3709173e Signed-off-by: Salil Mehta --- hw/acpi/cpu.c | 38 ++++++++++++++++++++++++++++++++++---- include/hw/core/cpu.h | 1 + 2 files changed, 35 insertions(+), 4 deletions(-) diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index 9b03b4292e..23443f09a5 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -50,6 +50,18 @@ void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIO= STInfoList ***list) } } =20 +static bool check_cpu_enabled_status(DeviceState *dev) +{ + CPUClass *k =3D dev ? CPU_GET_CLASS(dev) : NULL; + CPUState *cpu =3D CPU(dev); + + if (cpu && (!k->cpu_enabled_status || k->cpu_enabled_status(cpu))) { + return true; + } + + return false; +} + static uint64_t cpu_hotplug_rd(void *opaque, hwaddr addr, unsigned size) { uint64_t val =3D 0; @@ -63,10 +75,11 @@ static uint64_t cpu_hotplug_rd(void *opaque, hwaddr add= r, unsigned size) cdev =3D &cpu_st->devs[cpu_st->selector]; switch (addr) { case ACPI_CPU_FLAGS_OFFSET_RW: /* pack and return is_* fields */ - val |=3D cdev->cpu ? 1 : 0; + val |=3D check_cpu_enabled_status(DEVICE(cdev->cpu)) ? 1 : 0; val |=3D cdev->is_inserting ? 2 : 0; val |=3D cdev->is_removing ? 4 : 0; val |=3D cdev->fw_remove ? 16 : 0; + val |=3D cdev->cpu ? 32 : 0; trace_cpuhp_acpi_read_flags(cpu_st->selector, val); break; case ACPI_CPU_CMD_DATA_OFFSET_RW: @@ -349,6 +362,7 @@ const VMStateDescription vmstate_cpu_hotplug =3D { #define CPU_REMOVE_EVENT "CRMV" #define CPU_EJECT_EVENT "CEJ0" #define CPU_FW_EJECT_EVENT "CEJF" +#define CPU_PRESENT "CPRS" =20 void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures = opts, build_madt_cpu_fn build_madt_cpu, hwaddr base_addr, @@ -409,7 +423,9 @@ void build_cpus_aml(Aml *table, MachineState *machine, = CPUHotplugFeatures opts, aml_append(field, aml_named_field(CPU_EJECT_EVENT, 1)); /* tell firmware to do device eject, write only */ aml_append(field, aml_named_field(CPU_FW_EJECT_EVENT, 1)); - aml_append(field, aml_reserved_field(3)); + /* 1 if present, read only */ + aml_append(field, aml_named_field(CPU_PRESENT, 1)); + aml_append(field, aml_reserved_field(2)); aml_append(field, aml_named_field(CPU_COMMAND, 8)); aml_append(cpu_ctrl_dev, field); =20 @@ -439,6 +455,7 @@ void build_cpus_aml(Aml *table, MachineState *machine, = CPUHotplugFeatures opts, Aml *ctrl_lock =3D aml_name("%s.%s", cphp_res_path, CPU_LOCK); Aml *cpu_selector =3D aml_name("%s.%s", cphp_res_path, CPU_SELECTO= R); Aml *is_enabled =3D aml_name("%s.%s", cphp_res_path, CPU_ENABLED); + Aml *is_present =3D aml_name("%s.%s", cphp_res_path, CPU_PRESENT); Aml *cpu_cmd =3D aml_name("%s.%s", cphp_res_path, CPU_COMMAND); Aml *cpu_data =3D aml_name("%s.%s", cphp_res_path, CPU_DATA); Aml *ins_evt =3D aml_name("%s.%s", cphp_res_path, CPU_INSERT_EVENT= ); @@ -467,13 +484,26 @@ void build_cpus_aml(Aml *table, MachineState *machine= , CPUHotplugFeatures opts, { Aml *idx =3D aml_arg(0); Aml *sta =3D aml_local(0); + Aml *ifctx2; + Aml *else_ctx; =20 aml_append(method, aml_acquire(ctrl_lock, 0xFFFF)); aml_append(method, aml_store(idx, cpu_selector)); aml_append(method, aml_store(zero, sta)); - ifctx =3D aml_if(aml_equal(is_enabled, one)); + ifctx =3D aml_if(aml_equal(is_present, one)); { - aml_append(ifctx, aml_store(aml_int(0xF), sta)); + ifctx2 =3D aml_if(aml_equal(is_enabled, one)); + { + /* cpu is present and enabled */ + aml_append(ifctx2, aml_store(aml_int(0xF), sta)); + } + aml_append(ifctx, ifctx2); + else_ctx =3D aml_else(); + { + /* cpu is present but disabled */ + aml_append(else_ctx, aml_store(aml_int(0xD), sta)); + } + aml_append(ifctx, else_ctx); } aml_append(method, ifctx); aml_append(method, aml_release(ctrl_lock)); diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index e7de77dc6d..db8a6fbc6e 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -159,6 +159,7 @@ struct CPUClass { void (*query_cpu_fast)(CPUState *cpu, CpuInfoFast *value); int64_t (*get_arch_id)(CPUState *cpu); bool (*cpu_persistent_status)(CPUState *cpu); + bool (*cpu_enabled_status)(CPUState *cpu); void (*set_pc)(CPUState *cpu, vaddr value); vaddr (*get_pc)(CPUState *cpu); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); --=20 2.34.1