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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-431bd74f132sm97724275e9.0.2024.11.01.07.28.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 07:28:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1730471327; x=1731076127; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=76KrJrVxLWGUKTLdIPXIfzklJeCw9lpwmI0f/85N4u8=; b=bqt48wwlwtlRQiOs7c0pdvhI3uBUv5TSA0IHIJi0PYG2AOLfivN6Tbd0FhGXuNISJZ DP8ygk9VPrJMeOAOSRqnCVeMdSGYV4bbZULgUO3+f+msnOZ56zr43vovuXDmN63RKge9 dMynPCpvojd57e849MVxEjiQPnVDJVYX5xqKU3lhUY7eBaJmpoG2675GJePU5ZI9RarU FRS0u6ApgL+43ybKhQyeK7LDbZdnV6Eh/HHQGjVYXmxOWOy7ichqDNhkmvuxeHul5yZx w5EovmzEXFkdLaWPElHC2+bYFWCjoR27AVwjjBtrRlNdXg0npyaoyMcGMCoguLDgOMnJ cpHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730471327; x=1731076127; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=76KrJrVxLWGUKTLdIPXIfzklJeCw9lpwmI0f/85N4u8=; b=LTFA3QetwpI2DevVfFSeZ/x+8UNze0gZj9onh6dQqtgttN570cp/rs4symnNf1sWRW t2wptGiwL4/RARLP0s19dEjB1znuj96WfeYNAIsAeq4q9/OLgxOZhQIR6OmqowMjgk+e HPIVa71vQitiuocOQ67QQBUW/aIXaCi4ItXuTCqZ92QnQPm0YvZYgoM+viumT8JNroT9 lUYGrnSm1rv6bLfDjjeIFffc9BPTJ7boFjjjZQELo1Wzgj5GFd3wMYiOFSz3KNoswo37 cRRg7Ev/zfQQADEkF00vNj9O8+kW2Mve/cBnbesTSguj7CWvyk723ywf4Wz0sEMY5wMa 5dIQ== X-Forwarded-Encrypted: i=1; AJvYcCUhZnreJ6dPBNZezrYHWN0A+N7CjQGd+odo7SAcXkPFbID/GobS2hA1cwLUfyUXtb1098Cu2q9hk8YO@nongnu.org X-Gm-Message-State: AOJu0YyxlGqGjgxew6r2AcqyIWAEKeb0nTssugZFLnbL4AcJ1+9BH4Iq jre1n9joUeZrGOTPFvmu+TR/dzX9zIZlE9XmKkTGZ0kg9MkLK6enSNi3JGkxyCCJIgbPDy5rSOw Z X-Google-Smtp-Source: AGHT+IG0xEAsfafrNGWSg9K/+AxDx5t1AaUUUcXO/UI3vGKzemnU2hUAVppfYjGFmGlX01KR4pS14Q== X-Received: by 2002:a05:600c:4e8b:b0:431:40ca:ce44 with SMTP id 5b1f17b1804b1-4319ad34a44mr194985185e9.30.1730471327221; Fri, 01 Nov 2024 07:28:47 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/2] Revert "target/arm: Fix usage of MMU indexes when EL3 is AArch32" Date: Fri, 1 Nov 2024 14:28:44 +0000 Message-Id: <20241101142845.1712482-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101142845.1712482-1-peter.maydell@linaro.org> References: <20241101142845.1712482-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730471375967116600 Content-Type: text/plain; charset="utf-8" This reverts commit 4c2c0474693229c1f533239bb983495c5427784d. This commit tried to fix a problem with our usage of MMU indexes when EL3 is AArch32, using what it described as a "more complicated approach" where we share the same MMU index values for Secure PL1&0 and NonSecure PL1&0. In theory this should work, but the change didn't account for (at least) two things: (1) The design change means we need to flush the TLBs at any point where the CPU state flips from one to the other. We already flush the TLB when SCR.NS is changed, but we don't flush the TLB when we take an exception from NS PL1&0 into Mon or when we return from Mon to NS PL1&0, and the commit didn't add any code to do that. (2) The ATS12NS* address translate instructions allow Mon code (which is Secure) to do a stage 1+2 page table walk for NS. I thought this was OK because do_ats_write() does a page table walk which doesn't use the TLBs, so because it can pass both the MMU index and also an ARMSecuritySpace argument we can tell the table walk that we want NS stage1+2, not S. But that means that all the code within the ptw that needs to find e.g. the regime EL cannot do so only with an mmu_idx -- all these functions like regime_sctlr(), regime_el(), etc would need to pass both an mmu_idx and the security_space, so they can tell whether this is a translation regime controlled by EL1 or EL3 (and so whether to look at SCTLR.S or SCTLR.NS, etc). In particular, because regime_el() wasn't updated to look at the ARMSecuritySpace it would return 1 even when the CPU was in Monitor mode (and the controlling EL is 3). This meant that page table walks in Monitor mode would look at the wrong SCTLR, TCR, etc and would generally fault when they should not. Rather than trying to make the complicated changes needed to rescue the design of 4c2c04746932, we revert it in order to instead take the route that that commit describes as "the most straightforward" fix, where we add new MMU indexes EL30_0, EL30_3, EL30_3_PAN to correspond to "Secure PL1&0 at PL0", "Secure PL1&0 at PL1", and "Secure PL1&0 at PL1 with PAN". This revert will re-expose the "spurious alignment faults in Secure PL0" issue #2326; we'll fix it again in the next commit. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Tested-by: Thomas Huth --- target/arm/cpu.h | 31 +++++++++++++------------------ target/arm/internals.h | 27 ++++----------------------- target/arm/tcg/translate.h | 2 -- target/arm/helper.c | 34 +++++++++++----------------------- target/arm/ptw.c | 6 +----- target/arm/tcg/hflags.c | 4 ---- target/arm/tcg/translate-a64.c | 2 +- target/arm/tcg/translate.c | 9 ++++----- 8 files changed, 34 insertions(+), 81 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f065756c5c7..7674899109d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2785,7 +2785,8 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_syn= c); * + NonSecure PL1 & 0 stage 1 * + NonSecure PL1 & 0 stage 2 * + NonSecure PL2 - * + Secure PL1 & 0 + * + Secure PL0 + * + Secure PL1 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) * * For QEMU, an mmu_idx is not quite the same as a translation regime beca= use: @@ -2803,39 +2804,37 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_s= ync); * The only use of stage 2 translations is either as part of an s1+2 * lookup or when loading the descriptors during a stage 1 page table = walk, * and in both those cases we don't use the TLB. - * 4. we want to be able to use the TLB for accesses done as part of a + * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" + * translation regimes, because they map reasonably well to each other + * and they can't both be active at the same time. + * 5. we want to be able to use the TLB for accesses done as part of a * stage1 page table walk, rather than having to walk the stage2 page * table over and over. - * 5. we need separate EL1/EL2 mmu_idx for handling the Privileged Access + * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access * Never (PAN) bit within PSTATE. - * 6. we fold together most secure and non-secure regimes for A-profile, + * 7. we fold together most secure and non-secure regimes for A-profile, * because there are no banked system registers for aarch64, so the * process of switching between secure and non-secure is * already heavyweight. - * 7. we cannot fold together Stage 2 Secure and Stage 2 NonSecure, + * 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure, * because both are in use simultaneously for Secure EL2. * * This gives us the following list of cases: * - * EL0 EL1&0 stage 1+2 (or AArch32 PL0 PL1&0 stage 1+2) - * EL1 EL1&0 stage 1+2 (or AArch32 PL1 PL1&0 stage 1+2) - * EL1 EL1&0 stage 1+2 +PAN (or AArch32 PL1 PL1&0 stage 1+2 +PAN) + * EL0 EL1&0 stage 1+2 (aka NS PL0) + * EL1 EL1&0 stage 1+2 (aka NS PL1) + * EL1 EL1&0 stage 1+2 +PAN * EL0 EL2&0 * EL2 EL2&0 * EL2 EL2&0 +PAN * EL2 (aka NS PL2) - * EL3 (not used when EL3 is AArch32) + * EL3 (aka S PL1) * Stage2 Secure * Stage2 NonSecure * plus one TLB per Physical address space: S, NS, Realm, Root * * for a total of 14 different mmu_idx. * - * Note that when EL3 is AArch32, the usage is potentially confusing - * because the MMU indexes are named for their AArch64 use, so code - * using the ARMMMUIdx_E10_1 might be at EL3, not EL1. This is because - * Secure PL1 is always at EL3. - * * R profile CPUs have an MPU, but can use the same set of MMU indexes * as A profile. They only need to distinguish EL0 and EL1 (and * EL2 for cores like the Cortex-R52). @@ -3128,10 +3127,6 @@ FIELD(TBFLAG_A32, NS, 10, 1) * This requires an SME trap from AArch32 mode when using NEON. */ FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) -/* - * Indicates whether we are in the Secure PL1&0 translation regime - */ -FIELD(TBFLAG_A32, S_PL1_0, 12, 1) =20 /* * Bit usage when in AArch32 state, for M-profile only. diff --git a/target/arm/internals.h b/target/arm/internals.h index 299a96a81a7..aaa9b92faa9 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -275,20 +275,6 @@ FIELD(CNTHCTL, CNTPMASK, 19, 1) #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */ #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */ =20 -/** - * arm_aa32_secure_pl1_0(): Return true if in Secure PL1&0 regime - * - * Return true if the CPU is in the Secure PL1&0 translation regime. - * This requires that EL3 exists and is AArch32 and we are currently - * Secure. If this is the case then the ARMMMUIdx_E10* apply and - * mean we are in EL3, not EL1. - */ -static inline bool arm_aa32_secure_pl1_0(CPUARMState *env) -{ - return arm_feature(env, ARM_FEATURE_EL3) && - !arm_el_is_aa64(env, 3) && arm_is_secure(env); -} - /** * raise_exception: Raise the specified exception. * Raise a guest exception with the specified value, syndrome register @@ -841,12 +827,7 @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_i= dx) return mmu_idx | ARM_MMU_IDX_A; } =20 -/** - * Return the exception level we're running at if our current MMU index - * is @mmu_idx. @s_pl1_0 should be true if this is the AArch32 - * Secure PL1&0 translation regime. - */ -int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx, bool s_pl1_0); +int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); =20 /* Return the MMU index for a v7M CPU in the specified security state */ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); @@ -941,11 +922,11 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) return 3; case ARMMMUIdx_E10_0: case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: + return arm_el_is_aa64(env, 3) || !arm_is_secure_below_el3(env) ? 1= : 3; case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: - return arm_el_is_aa64(env, 3) || !arm_is_secure_below_el3(env) ? 1= : 3; + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 5a2e10d64d5..20cd0e851c4 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -165,8 +165,6 @@ typedef struct DisasContext { uint8_t gm_blocksize; /* True if the current insn_start has been updated. */ bool insn_start_updated; - /* True if this is the AArch32 Secure PL1&0 translation regime */ - bool s_pl1_0; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ int c15_cpar; /* Offset from VNCR_EL2 when FEAT_NV2 redirects this reg to memory */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 0a731a38e8f..0900034d42a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3701,7 +3701,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, */ format64 =3D arm_s1_regime_using_lpae_format(env, mmu_idx); =20 - if (arm_feature(env, ARM_FEATURE_EL2) && !arm_aa32_secure_pl1_0(en= v)) { + if (arm_feature(env, ARM_FEATURE_EL2)) { if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D ARMMMUIdx_E10_1 || mmu_idx =3D=3D ARMMMUIdx_E10_1_PAN) { @@ -3775,11 +3775,13 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) case 0: /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP= */ switch (el) { + case 3: + mmu_idx =3D ARMMMUIdx_E3; + break; case 2: g_assert(ss !=3D ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit o= nly */ /* fall through */ case 1: - case 3: if (ri->crm =3D=3D 9 && arm_pan_enabled(env)) { mmu_idx =3D ARMMMUIdx_Stage1_E1_PAN; } else { @@ -11860,11 +11862,8 @@ void arm_cpu_do_interrupt(CPUState *cs) =20 uint64_t arm_sctlr(CPUARMState *env, int el) { - if (arm_aa32_secure_pl1_0(env)) { - /* In Secure PL1&0 SCTLR_S is always controlling */ - el =3D 3; - } else if (el =3D=3D 0) { - /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ + /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ + if (el =3D=3D 0) { ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, 0); el =3D mmu_idx =3D=3D ARMMMUIdx_E20_0 ? 2 : 1; } @@ -12524,12 +12523,8 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 0; } =20 -/* - * Return the exception level we're running at if this is our mmu_idx. - * s_pl1_0 should be true if this is the AArch32 Secure PL1&0 translation - * regime. - */ -int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx, bool s_pl1_0) +/* Return the exception level we're running at if this is our mmu_idx */ +int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) { if (mmu_idx & ARM_MMU_IDX_M) { return mmu_idx & ARM_MMU_IDX_M_PRIV; @@ -12541,7 +12536,7 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx, bool s_pl1= _0) return 0; case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: - return s_pl1_0 ? 3 : 1; + return 1; case ARMMMUIdx_E2: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: @@ -12579,15 +12574,6 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) idx =3D ARMMMUIdx_E10_0; } break; - case 3: - /* - * AArch64 EL3 has its own translation regime; AArch32 EL3 - * uses the Secure PL1&0 translation regime. - */ - if (arm_el_is_aa64(env, 3)) { - return ARMMMUIdx_E3; - } - /* fall through */ case 1: if (arm_pan_enabled(env)) { idx =3D ARMMMUIdx_E10_1_PAN; @@ -12607,6 +12593,8 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) idx =3D ARMMMUIdx_E2; } break; + case 3: + return ARMMMUIdx_E3; default: g_assert_not_reached(); } diff --git a/target/arm/ptw.c b/target/arm/ptw.c index dd402683973..ba3dd38a729 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3607,11 +3607,7 @@ bool get_phys_addr(CPUARMState *env, vaddr address, case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E2: - if (arm_aa32_secure_pl1_0(env)) { - ss =3D ARMSS_Secure; - } else { - ss =3D arm_security_space_below_el3(env); - } + ss =3D arm_security_space_below_el3(env); break; case ARMMMUIdx_Stage2: /* diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index bab7822ef66..f03977b4b00 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -198,10 +198,6 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *e= nv, int fp_el, DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1); } =20 - if (arm_aa32_secure_pl1_0(env)) { - DP_TBFLAG_A32(flags, S_PL1_0, 1); - } - return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } =20 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index ec0b1ee2523..b2851ea5032 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -11690,7 +11690,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->tbii =3D EX_TBFLAG_A64(tb_flags, TBII); dc->tbid =3D EX_TBFLAG_A64(tb_flags, TBID); dc->tcma =3D EX_TBFLAG_A64(tb_flags, TCMA); - dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx, false); + dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); #endif diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index e2748ff2bb8..c5bc691d92b 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -7546,6 +7546,10 @@ static void arm_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) =20 core_mmu_idx =3D EX_TBFLAG_ANY(tb_flags, MMUIDX); dc->mmu_idx =3D core_to_arm_mmu_idx(env, core_mmu_idx); + dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); +#if !defined(CONFIG_USER_ONLY) + dc->user =3D (dc->current_el =3D=3D 0); +#endif dc->fp_excp_el =3D EX_TBFLAG_ANY(tb_flags, FPEXC_EL); dc->align_mem =3D EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il =3D EX_TBFLAG_ANY(tb_flags, PSTATE__IL); @@ -7576,12 +7580,7 @@ static void arm_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) } dc->sme_trap_nonstreaming =3D EX_TBFLAG_A32(tb_flags, SME_TRAP_NONSTREAMING); - dc->s_pl1_0 =3D EX_TBFLAG_A32(tb_flags, S_PL1_0); } - dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx, dc->s_pl1_0); -#if !defined(CONFIG_USER_ONLY) - dc->user =3D (dc->current_el =3D=3D 0); -#endif dc->lse2 =3D false; /* applies only to aarch64 */ dc->cp_regs =3D cpu->cp_regs; dc->features =3D env->features; --=20 2.34.1 From nobody Sat Nov 23 20:57:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-431bd74f132sm97724275e9.0.2024.11.01.07.28.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 07:28:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1730471328; x=1731076128; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VrCTcqwXaALCKdESItZxSyXzndGu9yu+QQloVCgUQ3I=; b=poRJgeqpmQ1e9bpj+JnomCiyk1LTCk+4lBD3wd1PhUM4HHU4ymq/QtxdoHcWhZwpyY R9bOJGmUZEtcuPBnXEfZcgc6cEGz+oZZ5MEqj561NRtC5wu0s8wa3NMs2RUoE+beEhg9 E5RlAxftySqlGfRDcM7mOUPT6yNgNSI5XfbdvDPCnP2YAPT+hxAAUKroSIxc8oo1yZ8O bDtE2lwBagAqX9Wfj2za9V+YbdBwbq6K7+CYkyFr5n1QiyIVC0fc3TCNkOhsbLA/k8WM urAtUCNJFx4NaGjx57Fz2UqFpnr4JtrGYc+tfI7f5GGflWgheYDAt0ajPknmJihIn3UO GmYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730471328; x=1731076128; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VrCTcqwXaALCKdESItZxSyXzndGu9yu+QQloVCgUQ3I=; b=TZ9hkUhOyoLT6A0BfBUwcoJd/YkrJV8TdYlBMtW1xRzH0oINwolo54+ShYHhAuz6V8 Z2MTDUuIUfYzaMsXgw2V2XPiufczngZ2dOlXk5UlkmZatGbVNLs+pDtts37etysoiOny npQTryigRVCSgtfgYrM253Eq+1m8M9cgeRiXO6j/Z7hxdE3F0ojhC2P0nZMR4BwVNyd5 KmMWl6387juUoyIb8S5YqOGbH3SVVNbQRZ8U6UJBZqC9GV90svdCoG9IPLz/9dryoyEi JeL5xtmTy44NqI51Ah3OSIiRhrzwZymC7jvEwfdjV/o+CKzbYNR/JVdWuMoqsCgLphSL LdHQ== X-Forwarded-Encrypted: i=1; AJvYcCUIQWH8LNieTP3AlpcilF64ut5WFB4Kmsu9ICahiPrVseg2HXBprbRLqtuOUfoJoOr9241eMuL2IAIf@nongnu.org X-Gm-Message-State: AOJu0YxKqU6pcLRJl9wo//XEa+teXItohLfU9/QOSZTwLezfLc4VO2Qz 17BlPVWbgCjVacO2xmyLQZJ5+rKizbqvBun3LNa5cz9V7O1K9nj+dEwjaANIMso= X-Google-Smtp-Source: AGHT+IFgM7Dy6yKqHhDVOrYvTxEM1NlisFeaAdh1Px/lyLEMeFDNQiaLZi9hfbrMML1bPkc+ui/E5A== X-Received: by 2002:a05:600c:1385:b0:42c:ae30:fc4d with SMTP id 5b1f17b1804b1-431bb977328mr96156655e9.7.1730471327750; Fri, 01 Nov 2024 07:28:47 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/2] target/arm: Add new MMU indexes for AArch32 Secure PL1&0 Date: Fri, 1 Nov 2024 14:28:45 +0000 Message-Id: <20241101142845.1712482-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101142845.1712482-1-peter.maydell@linaro.org> References: <20241101142845.1712482-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730471383724116600 Content-Type: text/plain; charset="utf-8" Our current usage of MMU indexes when EL3 is AArch32 is confused. Architecturally, when EL3 is AArch32, all Secure code runs under the Secure PL1&0 translation regime: * code at EL3, which might be Mon, or SVC, or any of the other privileged modes (PL1) * code at EL0 (Secure PL0) This is different from when EL3 is AArch64, in which case EL3 is its own translation regime, and EL1 and EL0 (whether AArch32 or AArch64) have their own regime. We claimed to be mapping Secure PL1 to our ARMMMUIdx_EL3, but didn't do anything special about Secure PL0, which meant it used the same ARMMMUIdx_EL10_0 that NonSecure PL0 does. This resulted in a bug where arm_sctlr() incorrectly picked the NonSecure SCTLR as the controlling register when in Secure PL0, which meant we were spuriously generating alignment faults because we were looking at the wrong SCTLR control bits. The use of ARMMMUIdx_EL3 for Secure PL1 also resulted in the bug that we wouldn't honour the PAN bit for Secure PL1, because there's no equivalent _PAN mmu index for it. Fix this by adding two new MMU indexes: * ARMMMUIdx_E30_0 is for Secure PL0 * ARMMMUIdx_E30_3_PAN is for Secure PL1 when PAN is enabled The existing ARMMMUIdx_E3 is used to mean "Secure PL1 without PAN" (and would be named ARMMMUIdx_E30_3 in an AArch32-centric scheme). These extra two indexes bring us up to the maximum of 16 that the core code can currently support. This commit: * adds the new MMU index handling to the various places where we deal in MMU index values * adds assertions that we aren't AArch32 EL3 in a couple of places that currently use the E10 indexes, to document why they don't also need to handle the E30 indexes * documents in a comment why regime_has_2_ranges() doesn't need updating Notes for backporting: this commit depends on the preceding revert of 4c2c04746932; that revert and this commit should probably be backported to everywhere that we originally backported 4c2c04746932. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2326 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Thomas Huth --- The regime_has_2_ranges() part is correct but does leave a minor beartrap for the future if we ever do for some reason need to identify "has 2 ranges" in an AArch32 codepath... --- target/arm/cpu.h | 31 ++++++++++++++++++------------- target/arm/internals.h | 16 ++++++++++++++-- target/arm/helper.c | 38 ++++++++++++++++++++++++++++++++++---- target/arm/ptw.c | 4 ++++ target/arm/tcg/op_helper.c | 14 +++++++++++++- target/arm/tcg/translate.c | 3 +++ 6 files changed, 86 insertions(+), 20 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7674899109d..283ea7358cf 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2785,8 +2785,7 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_syn= c); * + NonSecure PL1 & 0 stage 1 * + NonSecure PL1 & 0 stage 2 * + NonSecure PL2 - * + Secure PL0 - * + Secure PL1 + * + Secure PL1 & 0 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) * * For QEMU, an mmu_idx is not quite the same as a translation regime beca= use: @@ -2821,19 +2820,21 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_s= ync); * * This gives us the following list of cases: * - * EL0 EL1&0 stage 1+2 (aka NS PL0) - * EL1 EL1&0 stage 1+2 (aka NS PL1) - * EL1 EL1&0 stage 1+2 +PAN + * EL0 EL1&0 stage 1+2 (aka NS PL0 PL1&0 stage 1+2) + * EL1 EL1&0 stage 1+2 (aka NS PL1 PL1&0 stage 1+2) + * EL1 EL1&0 stage 1+2 +PAN (aka NS PL1 P1&0 stage 1+2 +PAN) * EL0 EL2&0 * EL2 EL2&0 * EL2 EL2&0 +PAN * EL2 (aka NS PL2) - * EL3 (aka S PL1) + * EL3 (aka AArch32 S PL1 PL1&0) + * AArch32 S PL0 PL1&0 (we call this EL30_0) + * AArch32 S PL1 PL1&0 +PAN (we call this EL30_3_PAN) * Stage2 Secure * Stage2 NonSecure * plus one TLB per Physical address space: S, NS, Realm, Root * - * for a total of 14 different mmu_idx. + * for a total of 16 different mmu_idx. * * R profile CPUs have an MPU, but can use the same set of MMU indexes * as A profile. They only need to distinguish EL0 and EL1 (and @@ -2897,6 +2898,8 @@ typedef enum ARMMMUIdx { ARMMMUIdx_E20_2_PAN =3D 5 | ARM_MMU_IDX_A, ARMMMUIdx_E2 =3D 6 | ARM_MMU_IDX_A, ARMMMUIdx_E3 =3D 7 | ARM_MMU_IDX_A, + ARMMMUIdx_E30_0 =3D 8 | ARM_MMU_IDX_A, + ARMMMUIdx_E30_3_PAN =3D 9 | ARM_MMU_IDX_A, =20 /* * Used for second stage of an S12 page table walk, or for descriptor @@ -2904,14 +2907,14 @@ typedef enum ARMMMUIdx { * are in use simultaneously for SecureEL2: the security state for * the S2 ptw is selected by the NS bit from the S1 ptw. */ - ARMMMUIdx_Stage2_S =3D 8 | ARM_MMU_IDX_A, - ARMMMUIdx_Stage2 =3D 9 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2_S =3D 10 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2 =3D 11 | ARM_MMU_IDX_A, =20 /* TLBs with 1-1 mapping to the physical address spaces. */ - ARMMMUIdx_Phys_S =3D 10 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_NS =3D 11 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_Root =3D 12 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_Realm =3D 13 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_S =3D 12 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_NS =3D 13 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Root =3D 14 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Realm =3D 15 | ARM_MMU_IDX_A, =20 /* * These are not allocated TLBs and are used only for AT system @@ -2950,6 +2953,8 @@ typedef enum ARMMMUIdxBit { TO_CORE_BIT(E20_2), TO_CORE_BIT(E20_2_PAN), TO_CORE_BIT(E3), + TO_CORE_BIT(E30_0), + TO_CORE_BIT(E30_3_PAN), TO_CORE_BIT(Stage2), TO_CORE_BIT(Stage2_S), =20 diff --git a/target/arm/internals.h b/target/arm/internals.h index aaa9b92faa9..185677f6fc7 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -871,7 +871,16 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu) } } =20 -/* Return true if this address translation regime has two ranges. */ +/* + * Return true if this address translation regime has two ranges. + * Note that this will not return the correct answer for AArch32 + * Secure PL1&0 (i.e. mmu indexes E3, E30_0, E30_3_PAN), but it is + * never called from a context where EL3 can be AArch32. (The + * correct return value for ARMMMUIdx_E3 would be different for + * that case, so we can't just make the function return the + * correct value anyway; we would need an extra "bool e3_is_aarch32" + * argument which all the current callsites would pass as 'false'.) + */ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) { switch (mmu_idx) { @@ -896,6 +905,7 @@ static inline bool regime_is_pan(CPUARMState *env, ARMM= MUIdx mmu_idx) case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_E30_3_PAN: return true; default: return false; @@ -919,10 +929,11 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) case ARMMMUIdx_E2: return 2; case ARMMMUIdx_E3: + case ARMMMUIdx_E30_0: + case ARMMMUIdx_E30_3_PAN: return 3; case ARMMMUIdx_E10_0: case ARMMMUIdx_Stage1_E0: - return arm_el_is_aa64(env, 3) || !arm_is_secure_below_el3(env) ? 1= : 3; case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E10_1: @@ -945,6 +956,7 @@ static inline bool regime_is_user(CPUARMState *env, ARM= MMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_E20_0: + case ARMMMUIdx_E30_0: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: diff --git a/target/arm/helper.c b/target/arm/helper.c index 0900034d42a..8c4f86f475a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -444,6 +444,9 @@ static int alle1_tlbmask(CPUARMState *env) * Note that the 'ALL' scope must invalidate both stage 1 and * stage 2 translations, whereas most other scopes only invalidate * stage 1 translations. + * + * For AArch32 this is only used for TLBIALLNSNH and VTTBR + * writes, so only needs to apply to NS PL1&0, not S PL1&0. */ return (ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_1_PAN | @@ -3776,7 +3779,11 @@ static void ats_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP= */ switch (el) { case 3: - mmu_idx =3D ARMMMUIdx_E3; + if (ri->crm =3D=3D 9 && arm_pan_enabled(env)) { + mmu_idx =3D ARMMMUIdx_E30_3_PAN; + } else { + mmu_idx =3D ARMMMUIdx_E3; + } break; case 2: g_assert(ss !=3D ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit o= nly */ @@ -3796,7 +3803,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ switch (el) { case 3: - mmu_idx =3D ARMMMUIdx_E10_0; + mmu_idx =3D ARMMMUIdx_E30_0; break; case 2: g_assert(ss !=3D ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit o= nly */ @@ -4906,11 +4913,14 @@ static int vae1_tlbmask(CPUARMState *env) uint64_t hcr =3D arm_hcr_el2_eff(env); uint16_t mask; =20 + assert(arm_feature(env, ARM_FEATURE_AARCH64)); + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { mask =3D ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_2_PAN | ARMMMUIdxBit_E20_0; } else { + /* This is AArch64 only, so we don't need to touch the EL30_x TLBs= */ mask =3D ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0; @@ -4949,6 +4959,8 @@ static int vae1_tlbbits(CPUARMState *env, uint64_t ad= dr) uint64_t hcr =3D arm_hcr_el2_eff(env); ARMMMUIdx mmu_idx; =20 + assert(arm_feature(env, ARM_FEATURE_AARCH64)); + /* Only the regime of the mmu_idx below is significant. */ if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { mmu_idx =3D ARMMMUIdx_E20_0; @@ -11862,10 +11874,20 @@ void arm_cpu_do_interrupt(CPUState *cs) =20 uint64_t arm_sctlr(CPUARMState *env, int el) { - /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ + /* Only EL0 needs to be adjusted for EL1&0 or EL2&0 or EL3&0 */ if (el =3D=3D 0) { ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, 0); - el =3D mmu_idx =3D=3D ARMMMUIdx_E20_0 ? 2 : 1; + switch (mmu_idx) { + case ARMMMUIdx_E20_0: + el =3D 2; + break; + case ARMMMUIdx_E30_0: + el =3D 3; + break; + default: + el =3D 1; + break; + } } return env->cp15.sctlr_el[el]; } @@ -12533,6 +12555,7 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_E10_0: case ARMMMUIdx_E20_0: + case ARMMMUIdx_E30_0: return 0; case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: @@ -12542,6 +12565,7 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) case ARMMMUIdx_E20_2_PAN: return 2; case ARMMMUIdx_E3: + case ARMMMUIdx_E30_3_PAN: return 3; default: g_assert_not_reached(); @@ -12570,6 +12594,9 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) hcr =3D arm_hcr_el2_eff(env); if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { idx =3D ARMMMUIdx_E20_0; + } else if (arm_is_secure_below_el3(env) && + !arm_el_is_aa64(env, 3)) { + idx =3D ARMMMUIdx_E30_0; } else { idx =3D ARMMMUIdx_E10_0; } @@ -12594,6 +12621,9 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) } break; case 3: + if (!arm_el_is_aa64(env, 3) && arm_pan_enabled(env)) { + return ARMMMUIdx_E30_3_PAN; + } return ARMMMUIdx_E3; default: g_assert_not_reached(); diff --git a/target/arm/ptw.c b/target/arm/ptw.c index ba3dd38a729..98499495085 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -280,6 +280,8 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx, case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_E2: case ARMMMUIdx_E3: + case ARMMMUIdx_E30_0: + case ARMMMUIdx_E30_3_PAN: break; =20 case ARMMMUIdx_Phys_S: @@ -3635,6 +3637,8 @@ bool get_phys_addr(CPUARMState *env, vaddr address, ss =3D ARMSS_Secure; break; case ARMMMUIdx_E3: + case ARMMMUIdx_E30_0: + case ARMMMUIdx_E30_3_PAN: if (arm_feature(env, ARM_FEATURE_AARCH64) && cpu_isar_feature(aa64_rme, env_archcpu(env))) { ss =3D ARMSS_Root; diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index c083e5cfb87..1ecb4659889 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -912,7 +912,19 @@ void HELPER(tidcp_el0)(CPUARMState *env, uint32_t synd= rome) { /* See arm_sctlr(), but we also need the sctlr el. */ ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, 0); - int target_el =3D mmu_idx =3D=3D ARMMMUIdx_E20_0 ? 2 : 1; + int target_el; + + switch (mmu_idx) { + case ARMMMUIdx_E20_0: + target_el =3D 2; + break; + case ARMMMUIdx_E30_0: + target_el =3D 3; + break; + default: + target_el =3D 1; + break; + } =20 /* * The bit is not valid unless the target el is aa64, but since the diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index c5bc691d92b..9ee761fc647 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -228,6 +228,9 @@ static inline int get_a32_user_mem_index(DisasContext *= s) */ switch (s->mmu_idx) { case ARMMMUIdx_E3: + case ARMMMUIdx_E30_0: + case ARMMMUIdx_E30_3_PAN: + return arm_to_core_mmu_idx(ARMMMUIdx_E30_0); case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */ case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: --=20 2.34.1