From nobody Thu Nov 14 18:03:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1730449066; cv=none; d=zohomail.com; s=zohoarc; b=hOQhruDr46n1MbpMdggqCjrQ8orAH+g+ZbQrU/GsqNm5eMLyetD253+sBNP0jyY3XFdu0BovU+iIH1PCYqHJZnbQa3+xEXp5kX5MdPhr/EYafFcJ2/GFXTHesekNoWOAWF5xSoqoYU5IqRuWaseSJWVYJJV9yHkrxhXiRj/7vL0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730449066; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qviPWeR044cXdS5udTXsEKPmpBKES18daBHsN4CzlEo=; b=PpXI1MpE1RjuNkPxQo+UAIyabOKLOlY7EFpZfHuU3eUJ1ggsidM3kYxxBOaWmJnx5SMsRoc9MGS6R6a/Sr6EJ4hHdNePtfFgpBnWAEM0DaErF60Kwa5tS2oG1N4mWxzWB4KIVvCKSZFikB0rAU6beWUMNSPsWimKhag7UoKH+0Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1730449066961903.7566033099287; Fri, 1 Nov 2024 01:17:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t6mpw-0005DX-Vd; Fri, 01 Nov 2024 04:16:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6mpl-00057A-Au; Fri, 01 Nov 2024 04:16:41 -0400 Received: from mgamail.intel.com ([192.198.163.16]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6mpj-0001QQ-K4; Fri, 01 Nov 2024 04:16:41 -0400 Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2024 01:16:38 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa003.fm.intel.com with ESMTP; 01 Nov 2024 01:16:33 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730449000; x=1761985000; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bCnGCo7lhItXTGaZkRo+zcrebUj+4UEX/OLY4d7GGMM=; b=FobMbu4Xukni446pNBuNVq1zamC+r/Snoqbwyt/K4reaxODwK43XrR4E kB1eoChzqEVd8lhrdby4qxJek2KPgEp5Cpfw/8qCPRzaHd+lvFYXsQqiw yMGqv2Ke6Blw6dYU6yavtEz/4XlNFlFqtU+tvBOGlZHAf/+JdlkX1J5ki iRB9b4caIyLs0mmvKHoFEPHqOKGuC45Y8/LoHOfP05SdkWUGbGs6WcM2N v9KagM3A7oE3j8uMruL/WNhZzV+IOQiIHnR0lQQypcu+G6npGDr7KvlfB gBSgbbGGjJcbXmO5dkoPnXWoIVVIUYERNQC9USTnVeItD7U8e6KK+l125 A==; X-CSE-ConnectionGUID: DjnV6ChiQg20D6PcXHt0lw== X-CSE-MsgGUID: 6jroPtkeT4SO6BwkTnMNhw== X-IronPort-AV: E=McAfee;i="6700,10204,11242"; a="17846079" X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="17846079" X-CSE-ConnectionGUID: UjbTBaHpTeWvuNuNrNxO0w== X-CSE-MsgGUID: wPlBlOj8Sd6HAXnmqU/Jng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="86834675" From: Zhao Liu To: =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Cc: Yongwei Ma Subject: [PATCH v5 7/9] i386/cpu: Update cache topology with machine's configuration Date: Fri, 1 Nov 2024 16:33:29 +0800 Message-Id: <20241101083331.340178-8-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101083331.340178-1-zhao1.liu@intel.com> References: <20241101083331.340178-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.366, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730449068267116600 Content-Type: text/plain; charset="utf-8" User will configure smp cache topology via -machine smp-cache. For this case, update the x86 CPUs' cache topology with user's configuration in MachineState. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Changes since Patch v3: * Updated MachineState.smp_cache to consume "default" level and did a check to ensure topological hierarchical relationships are correct. --- target/i386/cpu.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 09aaed95a856..1cf4cda1e647 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7753,6 +7753,64 @@ static void x86_cpu_hyperv_realize(X86CPU *cpu) cpu->hyperv_limits[2] =3D 0; } =20 +#ifndef CONFIG_USER_ONLY +static bool x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu, + Error **errp) +{ + CPUX86State *env =3D &cpu->env; + CpuTopologyLevel level; + + level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D); + if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l1d_cache->share_level =3D level; + env->cache_info_amd.l1d_cache->share_level =3D level; + } else { + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, + env->cache_info_cpuid4.l1d_cache->share_level); + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, + env->cache_info_amd.l1d_cache->share_level); + } + + level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I); + if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l1i_cache->share_level =3D level; + env->cache_info_amd.l1i_cache->share_level =3D level; + } else { + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, + env->cache_info_cpuid4.l1i_cache->share_level); + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, + env->cache_info_amd.l1i_cache->share_level); + } + + level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2); + if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l2_cache->share_level =3D level; + env->cache_info_amd.l2_cache->share_level =3D level; + } else { + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, + env->cache_info_cpuid4.l2_cache->share_level); + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, + env->cache_info_amd.l2_cache->share_level); + } + + level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3); + if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l3_cache->share_level =3D level; + env->cache_info_amd.l3_cache->share_level =3D level; + } else { + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, + env->cache_info_cpuid4.l3_cache->share_level); + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, + env->cache_info_amd.l3_cache->share_level); + } + + if (!machine_check_smp_cache(ms, errp)) { + return false; + } + return true; +} +#endif + static void x86_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -7977,6 +8035,15 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) =20 #ifndef CONFIG_USER_ONLY MachineState *ms =3D MACHINE(qdev_get_machine()); + + /* + * TODO: Add a SMPCompatProps.has_caches flag to avoid useless updates + * if user didn't set smp_cache. + */ + if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { + return; + } + qemu_register_reset(x86_cpu_machine_reset_cb, cpu); =20 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { --=20 2.34.1