From nobody Thu Nov 14 17:42:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1730449052; cv=none; d=zohomail.com; s=zohoarc; b=R5sOiWFoJ4LIbaP/Y3A15h3y+38spiMll5L4LM/KlnroXRMlg4qcC6+SHWl/R+U6WBLDCtBM5WnHlTh2793wfgWJduWZdaFNkmMBR0Uy5VhVVNjs/g4Nv+s0YhkuoBRdMQcMbkWFjKTfgGIBaYXRMvfQyLBVbDtfwF1/X3Ah1yY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730449052; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0iFY51lH1D0hyX3RZp+N+Kc+7Fdj3kVCkhSxBN80RyE=; b=lKXXwZ5O0s/d6MsJ74pPlMGXv4kz8UF4MPtSB2Rs5CbU5OESJCJM0r4ELbfadEvTXnyXR80egrHVNiRjwoFavnJTFOnHn3S4xXHA4R+0p8WH94xg51e3Dh03HDyhLvwSrQ331cFtI/M/KS34KyxytMiaalqa3uTe6Rf067Z7m4c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1730449052055536.1324565952922; Fri, 1 Nov 2024 01:17:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t6mpY-0004uq-O4; Fri, 01 Nov 2024 04:16:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6mpV-0004qy-3X; Fri, 01 Nov 2024 04:16:25 -0400 Received: from mgamail.intel.com ([192.198.163.16]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6mpT-0001QQ-Cr; Fri, 01 Nov 2024 04:16:24 -0400 Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2024 01:16:22 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa003.fm.intel.com with ESMTP; 01 Nov 2024 01:16:16 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730448984; x=1761984984; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E+zkEptv6x8nT44rXYHjEFJL+24l6aO0fCh+CMO/upA=; b=N+Djl/DYimZ5O7JZxRb0c6UzqNhkhm6Us2hXIEJgWUz5O8kJcbeO4dqb 56YVvyM8MFxNgA7g1xX9nYrdp8Hx2x5PR/nxC8K/NEwX+kgZAnZFT6wsO NurS9S6wLMl/hb8Pu9I2+agw8pOd141RZa/sB0C1bIywWVgZGztfYQIJz xMg4Ay44Xwv5wLR4DWAWv0//6YpFRRJ+U+Lv4TsAmn/KRD/KZCHpDeCUw XturGG0cw+BebTlgN2YBUsfkO+QT8DL0xR11fmWeAM7FAiCY94Zznao/w BCEFR6OrN1HDtY1TZO722qLTxYHKY5FivSPijWEvWj4S1h/iwUfHAkVyl A==; X-CSE-ConnectionGUID: dw+hTohTRm+9+A9SgBbz/A== X-CSE-MsgGUID: W7T+RrhzT2G0wuvAdh16aA== X-IronPort-AV: E=McAfee;i="6700,10204,11242"; a="17846045" X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="17846045" X-CSE-ConnectionGUID: lbUxUVPyRUaFO+h8PpQtzg== X-CSE-MsgGUID: j7+CQvoERvCthoCj5OUWJA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="86834611" From: Zhao Liu To: =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Cc: Yongwei Ma Subject: [PATCH v5 4/9] hw/core: Check smp cache topology support for machine Date: Fri, 1 Nov 2024 16:33:26 +0800 Message-Id: <20241101083331.340178-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101083331.340178-1-zhao1.liu@intel.com> References: <20241101083331.340178-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.366, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730449054490116600 Content-Type: text/plain; charset="utf-8" Add cache_supported flags in SMPCompatProps to allow machines to configure various caches support. And check the compatibility of the cache properties with the machine support in machine_parse_smp_cache(). Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Changes since Patch v3: * Dropped cache level check because if some fields is marked as default, then we can't guarentee the hierarchies are correct. (Daniel) --- hw/core/machine-smp.c | 41 +++++++++++++++++++++++++++++++++++++++++ include/hw/boards.h | 3 +++ 2 files changed, 44 insertions(+) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index c6d90cd6d413..ebb7a134a7be 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -261,10 +261,32 @@ void machine_parse_smp_config(MachineState *ms, } } =20 +static bool machine_check_topo_support(MachineState *ms, + CpuTopologyLevel topo, + Error **errp) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + + if ((topo =3D=3D CPU_TOPOLOGY_LEVEL_MODULE && !mc->smp_props.modules_s= upported) || + (topo =3D=3D CPU_TOPOLOGY_LEVEL_CLUSTER && !mc->smp_props.clusters= _supported) || + (topo =3D=3D CPU_TOPOLOGY_LEVEL_DIE && !mc->smp_props.dies_support= ed) || + (topo =3D=3D CPU_TOPOLOGY_LEVEL_BOOK && !mc->smp_props.books_suppo= rted) || + (topo =3D=3D CPU_TOPOLOGY_LEVEL_DRAWER && !mc->smp_props.drawers_s= upported)) { + error_setg(errp, + "Invalid topology level: %s. " + "The topology level is not supported by this machine", + CpuTopologyLevel_str(topo)); + return false; + } + + return true; +} + bool machine_parse_smp_cache(MachineState *ms, const SmpCachePropertiesList *caches, Error **errp) { + MachineClass *mc =3D MACHINE_GET_CLASS(ms); const SmpCachePropertiesList *node; DECLARE_BITMAP(caches_bitmap, CACHE_LEVEL_AND_TYPE__MAX); =20 @@ -283,6 +305,25 @@ bool machine_parse_smp_cache(MachineState *ms, set_bit(node->value->cache, caches_bitmap); } =20 + for (int i =3D 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { + const SmpCacheProperties *props =3D &ms->smp_cache.props[i]; + + /* + * Reject non "default" topology level if the cache isn't + * supported by the machine. + */ + if (props->topology !=3D CPU_TOPOLOGY_LEVEL_DEFAULT && + !mc->smp_props.cache_supported[props->cache]) { + error_setg(errp, + "%s cache topology not supported by this machine", + CacheLevelAndType_str(node->value->cache)); + return false; + } + + if (!machine_check_topo_support(ms, props->topology, errp)) { + return false; + } + } return true; } =20 diff --git a/include/hw/boards.h b/include/hw/boards.h index f12a727b4008..cda12070fc52 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -153,6 +153,8 @@ typedef struct { * @books_supported - whether books are supported by the machine * @drawers_supported - whether drawers are supported by the machine * @modules_supported - whether modules are supported by the machine + * @cache_supported - whether cache (l1d, l1i, l2 and l3) configuration are + * supported by the machine */ typedef struct { bool prefer_sockets; @@ -162,6 +164,7 @@ typedef struct { bool books_supported; bool drawers_supported; bool modules_supported; + bool cache_supported[CACHE_LEVEL_AND_TYPE__MAX]; } SMPCompatProps; =20 /** --=20 2.34.1