From nobody Thu Nov 14 18:00:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1730449062; cv=none; d=zohomail.com; s=zohoarc; b=JqxdJURFFUqBdOdEVgLmMgxX9onWwxKK9fD19l8682i43VWyDgvbBvdPIwxBmfQ/MoCOOjfd8vomTuhmWW7TrU77NaobtK63s9O/GDXUyfhbEODlIshvFyQcBpFHcRA1XaTwkQTDVOpmdICO5dCBKx+77tZomydKIg9wzzYrHC4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730449062; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=6TqdVHNe+cYtf3vp/W3GIXN2Swj7XvScw+JTDhzIZEI=; b=c9PifkL9uuAwJ2RoYzuPt2f7/7pJIWhCariyiT850KU2zBc4iLzE4fP6J+BopoF/3zIFDhiSA0VrIxAVlrH4L738apmd06k8UdglNTT7/2T7tXnQn01TiLuWNYQ5nCzgJ13JwyTOKJEp2aOsztytlkDxC/CwfOQA1W1aeyXDpSg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1730449062059107.16917778077016; Fri, 1 Nov 2024 01:17:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t6mpR-0004qD-5l; Fri, 01 Nov 2024 04:16:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6mpL-0004oh-Gb; Fri, 01 Nov 2024 04:16:15 -0400 Received: from mgamail.intel.com ([192.198.163.16]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6mpI-0001QQ-NG; Fri, 01 Nov 2024 04:16:15 -0400 Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2024 01:16:11 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa003.fm.intel.com with ESMTP; 01 Nov 2024 01:16:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730448973; x=1761984973; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cADX52QeG6aJc977vIccoDCUsDPglOq1brEwW5J7xMM=; b=gh/yNWxyr60SrFVxfCJBpcSbSjn3k/O1Qc3JykjFgpWG/vmuf9zPhX3o pIruAn2FJKh+m3cjcBdqNiBVTGN+FksQ1NeFNeBCeJVWL9bdEiOXeJbr9 QijF6x4IcV6B1lYwQXKeBrYhddVzsmtYzogqTSjoMcZjvKCZBmVU6W62H 7rXkknZ8id8vMtAtcbDmPBEgbTbw42c5y391nBvIb10hc/59bL1hOURVx E01SkELYGmpZ7gj+1BP291pOOMeTWNHaYBC0CQbZrr3zjl5x5nmAGI1LO TjSTqsAqjoo8TUGjgreJ095/yallukvW6bGIr6greDmwjrKH5JBGVu9cc w==; X-CSE-ConnectionGUID: UqIkZ/eMQqGkYVvScsdHVw== X-CSE-MsgGUID: yiz8vnhWQAi4zIs+w3hoIA== X-IronPort-AV: E=McAfee;i="6700,10204,11242"; a="17846024" X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="17846024" X-CSE-ConnectionGUID: HYMegiioTyCNjXpIU4gNHA== X-CSE-MsgGUID: YvcKsTwmRvi57eIKdrmIsQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="86834585" From: Zhao Liu To: =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Cc: Yongwei Ma Subject: [PATCH v5 2/9] hw/core: Make CPU topology enumeration arch-agnostic Date: Fri, 1 Nov 2024 16:33:24 +0800 Message-Id: <20241101083331.340178-3-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101083331.340178-1-zhao1.liu@intel.com> References: <20241101083331.340178-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.366, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730449064462116600 Cache topology needs to be defined based on CPU topology levels. Thus, define CPU topology enumeration in qapi/machine.json to make it generic for all architectures. To match the general topology naming style, rename CPU_TOPO_LEVEL_* to CPU_TOPOLOGY_LEVEL_*, and rename SMT and package levels to thread and socket. Also, enumerate additional topology levels for non-i386 arches, and add a CPU_TOPOLOGY_LEVEL_DEFAULT to help future smp-cache object to work with compatibility requirement of arch-specific cache topology models. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron Acked-by: Philippe Mathieu-Daud=C3=A9 --- Changes since Patch v3: * Dropped "invalid" level to avoid an unsettable option. (Daniel) --- hw/i386/x86-common.c | 4 +- include/hw/i386/topology.h | 23 ++---- qapi/machine-common.json | 44 +++++++++++- target/i386/cpu.c | 144 ++++++++++++++++++------------------- target/i386/cpu.h | 4 +- 5 files changed, 123 insertions(+), 96 deletions(-) diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index b86c38212eab..bc360a9ea44b 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -273,12 +273,12 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, =20 if (ms->smp.modules > 1) { env->nr_modules =3D ms->smp.modules; - set_bit(CPU_TOPO_LEVEL_MODULE, env->avail_cpu_topo); + set_bit(CPU_TOPOLOGY_LEVEL_MODULE, env->avail_cpu_topo); } =20 if (ms->smp.dies > 1) { env->nr_dies =3D ms->smp.dies; - set_bit(CPU_TOPO_LEVEL_DIE, env->avail_cpu_topo); + set_bit(CPU_TOPOLOGY_LEVEL_DIE, env->avail_cpu_topo); } =20 /* diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 48b43edc5a90..b2c8bf2de158 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -39,7 +39,7 @@ * CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_wid= th(). */ =20 - +#include "qapi/qapi-types-machine-common.h" #include "qemu/bitops.h" =20 /* @@ -62,22 +62,7 @@ typedef struct X86CPUTopoInfo { unsigned threads_per_core; } X86CPUTopoInfo; =20 -#define CPU_TOPO_LEVEL_INVALID CPU_TOPO_LEVEL_MAX - -/* - * CPUTopoLevel is the general i386 topology hierarchical representation, - * ordered by increasing hierarchical relationship. - * Its enumeration value is not bound to the type value of Intel (CPUID[0x= 1F]) - * or AMD (CPUID[0x80000026]). - */ -enum CPUTopoLevel { - CPU_TOPO_LEVEL_SMT, - CPU_TOPO_LEVEL_CORE, - CPU_TOPO_LEVEL_MODULE, - CPU_TOPO_LEVEL_DIE, - CPU_TOPO_LEVEL_PACKAGE, - CPU_TOPO_LEVEL_MAX, -}; +#define CPU_TOPOLOGY_LEVEL_INVALID CPU_TOPOLOGY_LEVEL__MAX =20 /* Return the bit width needed for 'count' IDs */ static unsigned apicid_bitwidth_for_count(unsigned count) @@ -213,8 +198,8 @@ static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUT= opoInfo *topo_info, */ static inline bool x86_has_extended_topo(unsigned long *topo_bitmap) { - return test_bit(CPU_TOPO_LEVEL_MODULE, topo_bitmap) || - test_bit(CPU_TOPO_LEVEL_DIE, topo_bitmap); + return test_bit(CPU_TOPOLOGY_LEVEL_MODULE, topo_bitmap) || + test_bit(CPU_TOPOLOGY_LEVEL_DIE, topo_bitmap); } =20 #endif /* HW_I386_TOPOLOGY_H */ diff --git a/qapi/machine-common.json b/qapi/machine-common.json index b64e4895cfd7..1a5687fb99fc 100644 --- a/qapi/machine-common.json +++ b/qapi/machine-common.json @@ -5,7 +5,7 @@ # See the COPYING file in the top-level directory. =20 ## -# =3D Machines S390 data types +# =3D Common machine types ## =20 ## @@ -18,3 +18,45 @@ ## { 'enum': 'S390CpuEntitlement', 'data': [ 'auto', 'low', 'medium', 'high' ] } + +## +# @CpuTopologyLevel: +# +# An enumeration of CPU topology levels. +# +# @thread: thread level, which would also be called SMT level or +# logical processor level. The @threads option in +# SMPConfiguration is used to configure the topology of this +# level. +# +# @core: core level. The @cores option in SMPConfiguration is used +# to configure the topology of this level. +# +# @module: module level. The @modules option in SMPConfiguration is +# used to configure the topology of this level. +# +# @cluster: cluster level. The @clusters option in SMPConfiguration +# is used to configure the topology of this level. +# +# @die: die level. The @dies option in SMPConfiguration is used to +# configure the topology of this level. +# +# @socket: socket level, which would also be called package level. +# The @sockets option in SMPConfiguration is used to configure +# the topology of this level. +# +# @book: book level. The @books option in SMPConfiguration is used +# to configure the topology of this level. +# +# @drawer: drawer level. The @drawers option in SMPConfiguration is +# used to configure the topology of this level. +# +# @default: default level. Some architectures will have default +# topology settings (e.g., cache topology), and this special +# level means following the architecture-specific settings. +# +# Since: 9.2 +## +{ 'enum': 'CpuTopologyLevel', + 'data': [ 'thread', 'core', 'module', 'cluster', 'die', + 'socket', 'book', 'drawer', 'default' ] } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ca13cf66a787..d46710a4030f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -238,23 +238,23 @@ static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *= cache) 0 /* Invalid value */) =20 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, - enum CPUTopoLevel share_level) + enum CpuTopologyLevel share_level) { uint32_t num_ids =3D 0; =20 switch (share_level) { - case CPU_TOPO_LEVEL_CORE: + case CPU_TOPOLOGY_LEVEL_CORE: num_ids =3D 1 << apicid_core_offset(topo_info); break; - case CPU_TOPO_LEVEL_DIE: + case CPU_TOPOLOGY_LEVEL_DIE: num_ids =3D 1 << apicid_die_offset(topo_info); break; - case CPU_TOPO_LEVEL_PACKAGE: + case CPU_TOPOLOGY_LEVEL_SOCKET: num_ids =3D 1 << apicid_pkg_offset(topo_info); break; default: /* - * Currently there is no use case for SMT and MODULE, so use + * Currently there is no use case for THREAD and MODULE, so use * assert directly to facilitate debugging. */ g_assert_not_reached(); @@ -303,19 +303,19 @@ static void encode_cache_cpuid4(CPUCacheInfo *cache, } =20 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, - enum CPUTopoLevel topo_level) + enum CpuTopologyLevel topo_level) { switch (topo_level) { - case CPU_TOPO_LEVEL_SMT: + case CPU_TOPOLOGY_LEVEL_THREAD: return 1; - case CPU_TOPO_LEVEL_CORE: + case CPU_TOPOLOGY_LEVEL_CORE: return topo_info->threads_per_core; - case CPU_TOPO_LEVEL_MODULE: + case CPU_TOPOLOGY_LEVEL_MODULE: return topo_info->threads_per_core * topo_info->cores_per_module; - case CPU_TOPO_LEVEL_DIE: + case CPU_TOPOLOGY_LEVEL_DIE: return topo_info->threads_per_core * topo_info->cores_per_module * topo_info->modules_per_die; - case CPU_TOPO_LEVEL_PACKAGE: + case CPU_TOPOLOGY_LEVEL_SOCKET: return topo_info->threads_per_core * topo_info->cores_per_module * topo_info->modules_per_die * topo_info->dies_per_pkg; default: @@ -325,18 +325,18 @@ static uint32_t num_threads_by_topo_level(X86CPUTopoI= nfo *topo_info, } =20 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, - enum CPUTopoLevel topo_level) + enum CpuTopologyLevel topo_lev= el) { switch (topo_level) { - case CPU_TOPO_LEVEL_SMT: + case CPU_TOPOLOGY_LEVEL_THREAD: return 0; - case CPU_TOPO_LEVEL_CORE: + case CPU_TOPOLOGY_LEVEL_CORE: return apicid_core_offset(topo_info); - case CPU_TOPO_LEVEL_MODULE: + case CPU_TOPOLOGY_LEVEL_MODULE: return apicid_module_offset(topo_info); - case CPU_TOPO_LEVEL_DIE: + case CPU_TOPOLOGY_LEVEL_DIE: return apicid_die_offset(topo_info); - case CPU_TOPO_LEVEL_PACKAGE: + case CPU_TOPOLOGY_LEVEL_SOCKET: return apicid_pkg_offset(topo_info); default: g_assert_not_reached(); @@ -344,18 +344,18 @@ static uint32_t apicid_offset_by_topo_level(X86CPUTop= oInfo *topo_info, return 0; } =20 -static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level) +static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) { switch (topo_level) { - case CPU_TOPO_LEVEL_INVALID: + case CPU_TOPOLOGY_LEVEL_INVALID: return CPUID_1F_ECX_TOPO_LEVEL_INVALID; - case CPU_TOPO_LEVEL_SMT: + case CPU_TOPOLOGY_LEVEL_THREAD: return CPUID_1F_ECX_TOPO_LEVEL_SMT; - case CPU_TOPO_LEVEL_CORE: + case CPU_TOPOLOGY_LEVEL_CORE: return CPUID_1F_ECX_TOPO_LEVEL_CORE; - case CPU_TOPO_LEVEL_MODULE: + case CPU_TOPOLOGY_LEVEL_MODULE: return CPUID_1F_ECX_TOPO_LEVEL_MODULE; - case CPU_TOPO_LEVEL_DIE: + case CPU_TOPOLOGY_LEVEL_DIE: return CPUID_1F_ECX_TOPO_LEVEL_DIE; default: /* Other types are not supported in QEMU. */ @@ -373,17 +373,17 @@ static void encode_topo_cpuid1f(CPUX86State *env, uin= t32_t count, unsigned long level, base_level, next_level; uint32_t num_threads_next_level, offset_next_level; =20 - assert(count <=3D CPU_TOPO_LEVEL_PACKAGE); + assert(count <=3D CPU_TOPOLOGY_LEVEL_SOCKET); =20 /* * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. - * The search starts from bit 0 (CPU_TOPO_LEVEL_SMT). + * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD). */ - level =3D CPU_TOPO_LEVEL_SMT; + level =3D CPU_TOPOLOGY_LEVEL_THREAD; base_level =3D level; for (int i =3D 0; i <=3D count; i++) { level =3D find_next_bit(env->avail_cpu_topo, - CPU_TOPO_LEVEL_PACKAGE, + CPU_TOPOLOGY_LEVEL_SOCKET, base_level); =20 /* @@ -391,20 +391,20 @@ static void encode_topo_cpuid1f(CPUX86State *env, uin= t32_t count, * and it just encodes the invalid level (all fields are 0) * into the last subleaf of 0x1f. */ - if (level =3D=3D CPU_TOPO_LEVEL_PACKAGE) { - level =3D CPU_TOPO_LEVEL_INVALID; + if (level =3D=3D CPU_TOPOLOGY_LEVEL_SOCKET) { + level =3D CPU_TOPOLOGY_LEVEL_INVALID; break; } /* Search the next level. */ base_level =3D level + 1; } =20 - if (level =3D=3D CPU_TOPO_LEVEL_INVALID) { + if (level =3D=3D CPU_TOPOLOGY_LEVEL_INVALID) { num_threads_next_level =3D 0; offset_next_level =3D 0; } else { next_level =3D find_next_bit(env->avail_cpu_topo, - CPU_TOPO_LEVEL_PACKAGE, + CPU_TOPOLOGY_LEVEL_SOCKET, level + 1); num_threads_next_level =3D num_threads_by_topo_level(topo_info, next_level); @@ -580,7 +580,7 @@ static CPUCacheInfo legacy_l1d_cache =3D { .sets =3D 64, .partitions =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ @@ -595,7 +595,7 @@ static CPUCacheInfo legacy_l1d_cache_amd =3D { .partitions =3D 1, .lines_per_tag =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 /* L1 instruction cache: */ @@ -609,7 +609,7 @@ static CPUCacheInfo legacy_l1i_cache =3D { .sets =3D 64, .partitions =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ @@ -624,7 +624,7 @@ static CPUCacheInfo legacy_l1i_cache_amd =3D { .partitions =3D 1, .lines_per_tag =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 /* Level 2 unified cache: */ @@ -638,7 +638,7 @@ static CPUCacheInfo legacy_l2_cache =3D { .sets =3D 4096, .partitions =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ @@ -648,7 +648,7 @@ static CPUCacheInfo legacy_l2_cache_cpuid2 =3D { .size =3D 2 * MiB, .line_size =3D 64, .associativity =3D 8, - .share_level =3D CPU_TOPO_LEVEL_INVALID, + .share_level =3D CPU_TOPOLOGY_LEVEL_INVALID, }; =20 =20 @@ -662,7 +662,7 @@ static CPUCacheInfo legacy_l2_cache_amd =3D { .associativity =3D 16, .sets =3D 512, .partitions =3D 1, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 /* Level 3 unified cache: */ @@ -678,7 +678,7 @@ static CPUCacheInfo legacy_l3_cache =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, - .share_level =3D CPU_TOPO_LEVEL_DIE, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, }; =20 /* TLB definitions: */ @@ -2085,7 +2085,7 @@ static const CPUCaches epyc_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2098,7 +2098,7 @@ static const CPUCaches epyc_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2109,7 +2109,7 @@ static const CPUCaches epyc_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2123,7 +2123,7 @@ static const CPUCaches epyc_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, - .share_level =3D CPU_TOPO_LEVEL_DIE, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, }, }; =20 @@ -2139,7 +2139,7 @@ static CPUCaches epyc_v4_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2152,7 +2152,7 @@ static CPUCaches epyc_v4_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2163,7 +2163,7 @@ static CPUCaches epyc_v4_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2177,7 +2177,7 @@ static CPUCaches epyc_v4_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, - .share_level =3D CPU_TOPO_LEVEL_DIE, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, }, }; =20 @@ -2193,7 +2193,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2206,7 +2206,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2217,7 +2217,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2231,7 +2231,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, - .share_level =3D CPU_TOPO_LEVEL_DIE, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, }, }; =20 @@ -2247,7 +2247,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2260,7 +2260,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2271,7 +2271,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2285,7 +2285,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, - .share_level =3D CPU_TOPO_LEVEL_DIE, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, }, }; =20 @@ -2301,7 +2301,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2314,7 +2314,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2325,7 +2325,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2339,7 +2339,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, - .share_level =3D CPU_TOPO_LEVEL_DIE, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, }, }; =20 @@ -2355,7 +2355,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2368,7 +2368,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2379,7 +2379,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2393,7 +2393,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, - .share_level =3D CPU_TOPO_LEVEL_DIE, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, }, }; =20 @@ -2409,7 +2409,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2422,7 +2422,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2433,7 +2433,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .partitions =3D 1, .sets =3D 2048, .lines_per_tag =3D 1, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2447,7 +2447,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, - .share_level =3D CPU_TOPO_LEVEL_DIE, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, }, }; =20 @@ -6591,7 +6591,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, =20 /* Share the cache at package level. */ *eax |=3D max_thread_ids_for_cache(&topo_info, - CPU_TOPO_LEVEL_PACKAGE) << 14; + CPU_TOPOLOGY_LEVEL_SOCKET) << 14; } } } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { @@ -8169,10 +8169,10 @@ static void x86_cpu_init_default_topo(X86CPU *cpu) env->nr_modules =3D 1; env->nr_dies =3D 1; =20 - /* SMT, core and package levels are set by default. */ - set_bit(CPU_TOPO_LEVEL_SMT, env->avail_cpu_topo); - set_bit(CPU_TOPO_LEVEL_CORE, env->avail_cpu_topo); - set_bit(CPU_TOPO_LEVEL_PACKAGE, env->avail_cpu_topo); + /* thread, core and socket levels are set by default. */ + set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); + set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); + set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); } =20 static void x86_cpu_initfn(Object *obj) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 59959b8b7a4d..00b23bc5d1f1 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1716,7 +1716,7 @@ typedef struct CPUCacheInfo { * Used to encode CPUID[4].EAX[bits 25:14] or * CPUID[0x8000001D].EAX[bits 25:14]. */ - enum CPUTopoLevel share_level; + CpuTopologyLevel share_level; } CPUCacheInfo; =20 =20 @@ -2051,7 +2051,7 @@ typedef struct CPUArchState { unsigned nr_modules; =20 /* Bitmap of available CPU topology levels for this CPU. */ - DECLARE_BITMAP(avail_cpu_topo, CPU_TOPO_LEVEL_MAX); + DECLARE_BITMAP(avail_cpu_topo, CPU_TOPOLOGY_LEVEL__MAX); } CPUX86State; =20 struct kvm_msrs; --=20 2.34.1