From nobody Thu Nov 14 18:11:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1730449122; cv=none; d=zohomail.com; s=zohoarc; b=DrAYSPV63MQH4JbiAv9N2tM1iFtL6iWfrzd/GF7yMdjyMsutO8KZTPH9vxERr7rlSsc5QZTgfg6NTtlRsLfBYmhcQ5S0xcp4LxDTkdvNwWs0RgAjCTjXX9gy9la9N2fQZzdFoVh7/akBuNMNSfmeY1m1ujKI2TJ2GjMRgakEaHQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730449122; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=dlnSKUGbAVnScE0hipLS5rVF9YVnuqQjBOa3jo8SatU=; b=GOHqRLXqaCdeU/cHCBQ4+lAYu+Qms2v3D2E707tiWGbwkR62ixhDhMCTljba1criHIYmzkQYeVqscZD11cRkWzv6ShRaL1A/mnGbXiup25jWVBrwioo3uu2A94QdZljKvM4UXNptfs3dVCJLsMoZ/AynlAC7E0qhkoapNWtkJSY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 173044912275618.27274313904752; Fri, 1 Nov 2024 01:18:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t6mq6-0005M4-KZ; Fri, 01 Nov 2024 04:17:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6mpx-0005ES-SW; Fri, 01 Nov 2024 04:16:55 -0400 Received: from mgamail.intel.com ([192.198.163.16]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6mpv-0001QQ-Cd; Fri, 01 Nov 2024 04:16:53 -0400 Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2024 01:16:50 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa003.fm.intel.com with ESMTP; 01 Nov 2024 01:16:44 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730449012; x=1761985012; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=se3A3A+kRvSwSAobc6tYFr7xeZZ8F/aVOqRAc4gXB10=; b=Oa73xaNgroSTh1S7dtucn+tBrDrlq2Remih3sbObqveh0bRThRnCcOL7 V5MWsxv36ngUVGOT9KCiA/ywzqXyhQtptXCSCYhKRfaKN5AWCH02ANGBA LC/NBORbMOpHg/lAkAb+MxCC4TFT/V4jJR3ibLlbo0ZCEPBtl9aF2RHzB csxR57jfqBK9MOmjOtNjAuZWt8HvKeELlsiVK6Lx0BUqjB3G4iV17/YXh DD4ASPkvZEGlYOtFyy8mx7hx4g8U5zoOIj5DecaCAsfQ0JIh8JAz5EAzd msYcTkcnmMWP4N0bJfofmhZ7Zczd+gqhqJXivgy8CG1IrVAWQErnIo/Aq A==; X-CSE-ConnectionGUID: vzOm0RRcTf2ZBncbIotCYw== X-CSE-MsgGUID: W5ac+AcgQ3iLv0JmK5AF/A== X-IronPort-AV: E=McAfee;i="6700,10204,11242"; a="17846103" X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="17846103" X-CSE-ConnectionGUID: MfnoaelzSjKKq1CkEaOG1g== X-CSE-MsgGUID: DHNWzy+0SfuGlV9pH5NKow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="86834736" From: Zhao Liu To: =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Subject: [PATCH v5 9/9] i386/cpu: add has_caches flag to check smp_cache configuration Date: Fri, 1 Nov 2024 16:33:31 +0800 Message-Id: <20241101083331.340178-10-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101083331.340178-1-zhao1.liu@intel.com> References: <20241101083331.340178-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.366, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730449124531116600 Content-Type: text/plain; charset="utf-8" From: Alireza Sanaee Add has_caches flag to SMPCompatProps, which helps in avoiding extra checks for every single layer of caches in x86 (and ARM in future). Signed-off-by: Alireza Sanaee Signed-off-by: Zhao Liu Reviewed-by: Jonathan Cameron --- Note: Picked from Alireza's series with the changes: * Moved the flag to SMPCompatProps with a new name "has_caches". This way, it remains consistent with the function and style of "has_clusters" in SMPCompatProps. * Dropped my previous TODO with the new flag. --- Changes since Patch v2: * Picked a new patch frome Alireza's ARM smp-cache series. --- hw/core/machine-smp.c | 2 ++ include/hw/boards.h | 3 +++ target/i386/cpu.c | 11 +++++------ 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index 640b2114b429..6ae7c4765402 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -324,6 +324,8 @@ bool machine_parse_smp_cache(MachineState *ms, return false; } } + + mc->smp_props.has_caches =3D true; return true; } =20 diff --git a/include/hw/boards.h b/include/hw/boards.h index e07fcf0983e1..2d650bbf13c4 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -156,6 +156,8 @@ typedef struct { * @modules_supported - whether modules are supported by the machine * @cache_supported - whether cache (l1d, l1i, l2 and l3) configuration are * supported by the machine + * @has_caches - whether cache properties are explicitly specified in the + * user provided smp-cache configuration */ typedef struct { bool prefer_sockets; @@ -166,6 +168,7 @@ typedef struct { bool drawers_supported; bool modules_supported; bool cache_supported[CACHE_LEVEL_AND_TYPE__MAX]; + bool has_caches; } SMPCompatProps; =20 /** diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1cf4cda1e647..49f19f896197 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8035,13 +8035,12 @@ static void x86_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 #ifndef CONFIG_USER_ONLY MachineState *ms =3D MACHINE(qdev_get_machine()); + MachineClass *mc =3D MACHINE_GET_CLASS(ms); =20 - /* - * TODO: Add a SMPCompatProps.has_caches flag to avoid useless updates - * if user didn't set smp_cache. - */ - if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { - return; + if (mc->smp_props.has_caches) { + if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { + return; + } } =20 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); --=20 2.34.1