From nobody Thu Nov 14 07:18:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1730449111; cv=none; d=zohomail.com; s=zohoarc; b=i3/vT3TXlEhLwa7+bDR2SufeEmSyqysGHsYaCicIYPbrk0f9Y+SHeoB1QDJPg5zR0/Y7nIUMA4bVqmtRFsXln4kP9/XD/LZ+e07qslflWtvOTIIrv/mq00Aa/+P0+4qfy1+s4j6a8vUL+tIUT50sO+RWv76h/6XNKpzNwt8EeyU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730449111; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=tHdWdtX/FL6m1+sUGMRuUXl0gcJWTfNyMeK/MYpCyrs=; b=YLPOlTlbqVgZ219aF+haH0IBfrSUeidgtFKneFsRkEx1XF6066kDWmK5Ah8OsrgbJljxMUHusQiLGCxRBBEtw7RF27EYutNoR6Mj99rinlu2ldDEByuDgp3NmwAMzIBJz0J4Zv9bwvk8/K/SzXADOb53XxTzLtMDFpWUxlGbB/M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1730449111378769.4248173121135; Fri, 1 Nov 2024 01:18:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t6mpW-0004ss-Dt; Fri, 01 Nov 2024 04:16:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6mpF-0004nc-5c; Fri, 01 Nov 2024 04:16:09 -0400 Received: from mgamail.intel.com ([192.198.163.16]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6mpC-0001O6-TV; Fri, 01 Nov 2024 04:16:08 -0400 Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2024 01:16:04 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa003.fm.intel.com with ESMTP; 01 Nov 2024 01:15:59 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730448967; x=1761984967; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=1dPWfn08NUNqOZ5PO7IBAQYY2uK5uWynR2m08PGiW3k=; b=bw4rN5AAvNfOIXYcRU/EkOXz68rRXH9AAa/hfeAehTlZgn7crrKxNS/B x8D3w2wJqVXQ85LAQkmvv4mN1IS4jisH6+zl4RUZANsfGjScI3Sjn1f6t rmElxnjibVJWRc1Q7OnF6H/SOj6XwKrLkxsJrUuA7D8mmg0esKHcoDa1n DpTvg6X0fKC4qQC0h9/8LThmg8eEVduKzsOCdJEr8GxRc7OkSLUZmjGSM hk+MRDaFpaUc4TehzqO8JKV4Rdidc06NWAkYEinEKwmpvqWFZDuQGox2b haWKQQSaECV6gwhwS9kc3gibHeYDyURaaLOApRqR8omHezYmhRpOBysfu Q==; X-CSE-ConnectionGUID: xgOUzljpRlK/ZrGprPOCBQ== X-CSE-MsgGUID: h+ALsnE1S4SORHx29wPjiw== X-IronPort-AV: E=McAfee;i="6700,10204,11242"; a="17846010" X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="17846010" X-CSE-ConnectionGUID: LUBhdBhGQwKOVlizCOoROQ== X-CSE-MsgGUID: R3gWI9O9St23dpn0CDALbw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="86834558" From: Zhao Liu To: =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Subject: [PATCH v5 1/9] i386/cpu: Don't enumerate the "invalid" CPU topology level Date: Fri, 1 Nov 2024 16:33:23 +0800 Message-Id: <20241101083331.340178-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101083331.340178-1-zhao1.liu@intel.com> References: <20241101083331.340178-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.366, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730449112308116600 Content-Type: text/plain; charset="utf-8" In the follow-up change, the CPU topology enumeration will be moved to QAPI. And considerring "invalid" should not be exposed to QAPI as an unsettable item, so, as a preparation for future changes, remove "invalid" level from the current CPU topology enumeration structure and define it by a macro instead. Due to the removal of the enumeration of "invalid", bit 0 of CPUX86State.avail_cpu_topo bitmap will no longer correspond to "invalid" level, but will start at the SMT level. Therefore, to honor this change, update the encoding rule for CPUID[0x1F]. Signed-off-by: Zhao Liu Reviewed-by: Jonathan Cameron --- Tested by the following cases to ensure 0x1f's behavior hasn't changed: -smp cpus=3D24,sockets=3D2,dies=3D3,modules=3D2,cores=3D2,threads=3D1 -smp cpus=3D24,sockets=3D2,dies=3D1,modules=3D3,cores=3D2,threads=3D2 -smp cpus=3D24,sockets=3D2,modules=3D3,cores=3D2,threads=3D2 -smp cpus=3D24,sockets=3D2,dies=3D3,modules=3D1,cores=3D2,threads=3D2 -smp cpus=3D24,sockets=3D2,dies=3D3,cores=3D2,threads=3D2 --- Changes since Patch v3: * Now commit to stop exposing "invalid" enumeration in QAPI. (Daniel) --- include/hw/i386/topology.h | 3 ++- target/i386/cpu.c | 13 ++++++++----- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index dff49fce1154..48b43edc5a90 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -62,6 +62,8 @@ typedef struct X86CPUTopoInfo { unsigned threads_per_core; } X86CPUTopoInfo; =20 +#define CPU_TOPO_LEVEL_INVALID CPU_TOPO_LEVEL_MAX + /* * CPUTopoLevel is the general i386 topology hierarchical representation, * ordered by increasing hierarchical relationship. @@ -69,7 +71,6 @@ typedef struct X86CPUTopoInfo { * or AMD (CPUID[0x80000026]). */ enum CPUTopoLevel { - CPU_TOPO_LEVEL_INVALID, CPU_TOPO_LEVEL_SMT, CPU_TOPO_LEVEL_CORE, CPU_TOPO_LEVEL_MODULE, diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3baa95481fbc..ca13cf66a787 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -370,20 +370,21 @@ static void encode_topo_cpuid1f(CPUX86State *env, uin= t32_t count, uint32_t *ecx, uint32_t *edx) { X86CPU *cpu =3D env_archcpu(env); - unsigned long level, next_level; + unsigned long level, base_level, next_level; uint32_t num_threads_next_level, offset_next_level; =20 - assert(count + 1 < CPU_TOPO_LEVEL_MAX); + assert(count <=3D CPU_TOPO_LEVEL_PACKAGE); =20 /* * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. - * The search starts from bit 1 (CPU_TOPO_LEVEL_INVALID + 1). + * The search starts from bit 0 (CPU_TOPO_LEVEL_SMT). */ - level =3D CPU_TOPO_LEVEL_INVALID; + level =3D CPU_TOPO_LEVEL_SMT; + base_level =3D level; for (int i =3D 0; i <=3D count; i++) { level =3D find_next_bit(env->avail_cpu_topo, CPU_TOPO_LEVEL_PACKAGE, - level + 1); + base_level); =20 /* * CPUID[0x1f] doesn't explicitly encode the package level, @@ -394,6 +395,8 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint3= 2_t count, level =3D CPU_TOPO_LEVEL_INVALID; break; } + /* Search the next level. */ + base_level =3D level + 1; } =20 if (level =3D=3D CPU_TOPO_LEVEL_INVALID) { --=20 2.34.1 From nobody Thu Nov 14 07:18:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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d="scan'208";a="86834585" From: Zhao Liu To: =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Cc: Yongwei Ma Subject: [PATCH v5 2/9] hw/core: Make CPU topology enumeration arch-agnostic Date: Fri, 1 Nov 2024 16:33:24 +0800 Message-Id: <20241101083331.340178-3-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101083331.340178-1-zhao1.liu@intel.com> References: <20241101083331.340178-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.366, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730449064462116600 Cache topology needs to be defined based on CPU topology levels. Thus, define CPU topology enumeration in qapi/machine.json to make it generic for all architectures. To match the general topology naming style, rename CPU_TOPO_LEVEL_* to CPU_TOPOLOGY_LEVEL_*, and rename SMT and package levels to thread and socket. Also, enumerate additional topology levels for non-i386 arches, and add a CPU_TOPOLOGY_LEVEL_DEFAULT to help future smp-cache object to work with compatibility requirement of arch-specific cache topology models. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron Acked-by: Philippe Mathieu-Daud=C3=A9 --- Changes since Patch v3: * Dropped "invalid" level to avoid an unsettable option. (Daniel) --- hw/i386/x86-common.c | 4 +- include/hw/i386/topology.h | 23 ++---- qapi/machine-common.json | 44 +++++++++++- target/i386/cpu.c | 144 ++++++++++++++++++------------------- target/i386/cpu.h | 4 +- 5 files changed, 123 insertions(+), 96 deletions(-) diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index b86c38212eab..bc360a9ea44b 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -273,12 +273,12 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, =20 if (ms->smp.modules > 1) { env->nr_modules =3D ms->smp.modules; - set_bit(CPU_TOPO_LEVEL_MODULE, env->avail_cpu_topo); + set_bit(CPU_TOPOLOGY_LEVEL_MODULE, env->avail_cpu_topo); } =20 if (ms->smp.dies > 1) { env->nr_dies =3D ms->smp.dies; - set_bit(CPU_TOPO_LEVEL_DIE, env->avail_cpu_topo); + set_bit(CPU_TOPOLOGY_LEVEL_DIE, env->avail_cpu_topo); } =20 /* diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 48b43edc5a90..b2c8bf2de158 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -39,7 +39,7 @@ * CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_wid= th(). */ =20 - +#include "qapi/qapi-types-machine-common.h" #include "qemu/bitops.h" =20 /* @@ -62,22 +62,7 @@ typedef struct X86CPUTopoInfo { unsigned threads_per_core; } X86CPUTopoInfo; =20 -#define CPU_TOPO_LEVEL_INVALID CPU_TOPO_LEVEL_MAX - -/* - * CPUTopoLevel is the general i386 topology hierarchical representation, - * ordered by increasing hierarchical relationship. - * Its enumeration value is not bound to the type value of Intel (CPUID[0x= 1F]) - * or AMD (CPUID[0x80000026]). - */ -enum CPUTopoLevel { - CPU_TOPO_LEVEL_SMT, - CPU_TOPO_LEVEL_CORE, - CPU_TOPO_LEVEL_MODULE, - CPU_TOPO_LEVEL_DIE, - CPU_TOPO_LEVEL_PACKAGE, - CPU_TOPO_LEVEL_MAX, -}; +#define CPU_TOPOLOGY_LEVEL_INVALID CPU_TOPOLOGY_LEVEL__MAX =20 /* Return the bit width needed for 'count' IDs */ static unsigned apicid_bitwidth_for_count(unsigned count) @@ -213,8 +198,8 @@ static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUT= opoInfo *topo_info, */ static inline bool x86_has_extended_topo(unsigned long *topo_bitmap) { - return test_bit(CPU_TOPO_LEVEL_MODULE, topo_bitmap) || - test_bit(CPU_TOPO_LEVEL_DIE, topo_bitmap); + return test_bit(CPU_TOPOLOGY_LEVEL_MODULE, topo_bitmap) || + test_bit(CPU_TOPOLOGY_LEVEL_DIE, topo_bitmap); } =20 #endif /* HW_I386_TOPOLOGY_H */ diff --git a/qapi/machine-common.json b/qapi/machine-common.json index b64e4895cfd7..1a5687fb99fc 100644 --- a/qapi/machine-common.json +++ b/qapi/machine-common.json @@ -5,7 +5,7 @@ # See the COPYING file in the top-level directory. =20 ## -# =3D Machines S390 data types +# =3D Common machine types ## =20 ## @@ -18,3 +18,45 @@ ## { 'enum': 'S390CpuEntitlement', 'data': [ 'auto', 'low', 'medium', 'high' ] } + +## +# @CpuTopologyLevel: +# +# An enumeration of CPU topology levels. +# +# @thread: thread level, which would also be called SMT level or +# logical processor level. The @threads option in +# SMPConfiguration is used to configure the topology of this +# level. +# +# @core: core level. The @cores option in SMPConfiguration is used +# to configure the topology of this level. +# +# @module: module level. The @modules option in SMPConfiguration is +# used to configure the topology of this level. +# +# @cluster: cluster level. The @clusters option in SMPConfiguration +# is used to configure the topology of this level. +# +# @die: die level. The @dies option in SMPConfiguration is used to +# configure the topology of this level. +# +# @socket: socket level, which would also be called package level. +# The @sockets option in SMPConfiguration is used to configure +# the topology of this level. +# +# @book: book level. The @books option in SMPConfiguration is used +# to configure the topology of this level. +# +# @drawer: drawer level. The @drawers option in SMPConfiguration is +# used to configure the topology of this level. +# +# @default: default level. Some architectures will have default +# topology settings (e.g., cache topology), and this special +# level means following the architecture-specific settings. +# +# Since: 9.2 +## +{ 'enum': 'CpuTopologyLevel', + 'data': [ 'thread', 'core', 'module', 'cluster', 'die', + 'socket', 'book', 'drawer', 'default' ] } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ca13cf66a787..d46710a4030f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -238,23 +238,23 @@ static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *= cache) 0 /* Invalid value */) =20 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, - enum CPUTopoLevel share_level) + enum CpuTopologyLevel share_level) { uint32_t num_ids =3D 0; =20 switch (share_level) { - case CPU_TOPO_LEVEL_CORE: + case CPU_TOPOLOGY_LEVEL_CORE: num_ids =3D 1 << apicid_core_offset(topo_info); break; - case CPU_TOPO_LEVEL_DIE: + case CPU_TOPOLOGY_LEVEL_DIE: num_ids =3D 1 << apicid_die_offset(topo_info); break; - case CPU_TOPO_LEVEL_PACKAGE: + case CPU_TOPOLOGY_LEVEL_SOCKET: num_ids =3D 1 << apicid_pkg_offset(topo_info); break; default: /* - * Currently there is no use case for SMT and MODULE, so use + * Currently there is no use case for THREAD and MODULE, so use * assert directly to facilitate debugging. */ g_assert_not_reached(); @@ -303,19 +303,19 @@ static void encode_cache_cpuid4(CPUCacheInfo *cache, } =20 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, - enum CPUTopoLevel topo_level) + enum CpuTopologyLevel topo_level) { switch (topo_level) { - case CPU_TOPO_LEVEL_SMT: + case CPU_TOPOLOGY_LEVEL_THREAD: return 1; - case CPU_TOPO_LEVEL_CORE: + case CPU_TOPOLOGY_LEVEL_CORE: return topo_info->threads_per_core; - case CPU_TOPO_LEVEL_MODULE: + case CPU_TOPOLOGY_LEVEL_MODULE: return topo_info->threads_per_core * topo_info->cores_per_module; - case CPU_TOPO_LEVEL_DIE: + case CPU_TOPOLOGY_LEVEL_DIE: return topo_info->threads_per_core * topo_info->cores_per_module * topo_info->modules_per_die; - case CPU_TOPO_LEVEL_PACKAGE: + case CPU_TOPOLOGY_LEVEL_SOCKET: return topo_info->threads_per_core * topo_info->cores_per_module * topo_info->modules_per_die * topo_info->dies_per_pkg; default: @@ -325,18 +325,18 @@ static uint32_t num_threads_by_topo_level(X86CPUTopoI= nfo *topo_info, } =20 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, - enum CPUTopoLevel topo_level) + enum CpuTopologyLevel topo_lev= el) { switch (topo_level) { - case CPU_TOPO_LEVEL_SMT: + case CPU_TOPOLOGY_LEVEL_THREAD: return 0; - case CPU_TOPO_LEVEL_CORE: + case CPU_TOPOLOGY_LEVEL_CORE: return apicid_core_offset(topo_info); - case CPU_TOPO_LEVEL_MODULE: + case CPU_TOPOLOGY_LEVEL_MODULE: return apicid_module_offset(topo_info); - case CPU_TOPO_LEVEL_DIE: + case CPU_TOPOLOGY_LEVEL_DIE: return apicid_die_offset(topo_info); - case CPU_TOPO_LEVEL_PACKAGE: + case CPU_TOPOLOGY_LEVEL_SOCKET: return apicid_pkg_offset(topo_info); default: g_assert_not_reached(); @@ -344,18 +344,18 @@ static uint32_t apicid_offset_by_topo_level(X86CPUTop= oInfo *topo_info, return 0; } =20 -static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level) +static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) { switch (topo_level) { - case CPU_TOPO_LEVEL_INVALID: + case CPU_TOPOLOGY_LEVEL_INVALID: return CPUID_1F_ECX_TOPO_LEVEL_INVALID; - case CPU_TOPO_LEVEL_SMT: + case CPU_TOPOLOGY_LEVEL_THREAD: return CPUID_1F_ECX_TOPO_LEVEL_SMT; - case CPU_TOPO_LEVEL_CORE: + case CPU_TOPOLOGY_LEVEL_CORE: return CPUID_1F_ECX_TOPO_LEVEL_CORE; - case CPU_TOPO_LEVEL_MODULE: + case CPU_TOPOLOGY_LEVEL_MODULE: return CPUID_1F_ECX_TOPO_LEVEL_MODULE; - case CPU_TOPO_LEVEL_DIE: + case CPU_TOPOLOGY_LEVEL_DIE: return CPUID_1F_ECX_TOPO_LEVEL_DIE; default: /* Other types are not supported in QEMU. */ @@ -373,17 +373,17 @@ static void encode_topo_cpuid1f(CPUX86State *env, uin= t32_t count, unsigned long level, base_level, next_level; uint32_t num_threads_next_level, offset_next_level; =20 - assert(count <=3D CPU_TOPO_LEVEL_PACKAGE); + assert(count <=3D CPU_TOPOLOGY_LEVEL_SOCKET); =20 /* * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. - * The search starts from bit 0 (CPU_TOPO_LEVEL_SMT). + * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD). */ - level =3D CPU_TOPO_LEVEL_SMT; + level =3D CPU_TOPOLOGY_LEVEL_THREAD; base_level =3D level; for (int i =3D 0; i <=3D count; i++) { level =3D find_next_bit(env->avail_cpu_topo, - CPU_TOPO_LEVEL_PACKAGE, + CPU_TOPOLOGY_LEVEL_SOCKET, base_level); =20 /* @@ -391,20 +391,20 @@ static void encode_topo_cpuid1f(CPUX86State *env, uin= t32_t count, * and it just encodes the invalid level (all fields are 0) * into the last subleaf of 0x1f. */ - if (level =3D=3D CPU_TOPO_LEVEL_PACKAGE) { - level =3D CPU_TOPO_LEVEL_INVALID; + if (level =3D=3D CPU_TOPOLOGY_LEVEL_SOCKET) { + level =3D CPU_TOPOLOGY_LEVEL_INVALID; break; } /* Search the next level. */ base_level =3D level + 1; } =20 - if (level =3D=3D CPU_TOPO_LEVEL_INVALID) { + if (level =3D=3D CPU_TOPOLOGY_LEVEL_INVALID) { num_threads_next_level =3D 0; offset_next_level =3D 0; } else { next_level =3D find_next_bit(env->avail_cpu_topo, - CPU_TOPO_LEVEL_PACKAGE, + CPU_TOPOLOGY_LEVEL_SOCKET, level + 1); num_threads_next_level =3D num_threads_by_topo_level(topo_info, next_level); @@ -580,7 +580,7 @@ static CPUCacheInfo legacy_l1d_cache =3D { .sets =3D 64, .partitions =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ @@ -595,7 +595,7 @@ static CPUCacheInfo legacy_l1d_cache_amd =3D { .partitions =3D 1, .lines_per_tag =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 /* L1 instruction cache: */ @@ -609,7 +609,7 @@ static CPUCacheInfo legacy_l1i_cache =3D { .sets =3D 64, .partitions =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ @@ -624,7 +624,7 @@ static CPUCacheInfo legacy_l1i_cache_amd =3D { .partitions =3D 1, .lines_per_tag =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 /* Level 2 unified cache: */ @@ -638,7 +638,7 @@ static CPUCacheInfo legacy_l2_cache =3D { .sets =3D 4096, .partitions =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ @@ -648,7 +648,7 @@ static CPUCacheInfo legacy_l2_cache_cpuid2 =3D { .size =3D 2 * MiB, .line_size =3D 64, .associativity =3D 8, - .share_level =3D CPU_TOPO_LEVEL_INVALID, + .share_level =3D CPU_TOPOLOGY_LEVEL_INVALID, }; =20 =20 @@ -662,7 +662,7 @@ static CPUCacheInfo legacy_l2_cache_amd =3D { .associativity =3D 16, .sets =3D 512, .partitions =3D 1, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 /* Level 3 unified cache: */ @@ -678,7 +678,7 @@ static CPUCacheInfo legacy_l3_cache =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, - .share_level =3D CPU_TOPO_LEVEL_DIE, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, }; =20 /* TLB definitions: */ @@ -2085,7 +2085,7 @@ static const CPUCaches epyc_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2098,7 +2098,7 @@ static const CPUCaches epyc_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2109,7 +2109,7 @@ static const CPUCaches epyc_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2123,7 +2123,7 @@ static const CPUCaches epyc_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, - .share_level =3D CPU_TOPO_LEVEL_DIE, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, }, }; =20 @@ -2139,7 +2139,7 @@ static CPUCaches epyc_v4_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2152,7 +2152,7 @@ static CPUCaches epyc_v4_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2163,7 +2163,7 @@ static CPUCaches epyc_v4_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2177,7 +2177,7 @@ static CPUCaches epyc_v4_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, - .share_level =3D CPU_TOPO_LEVEL_DIE, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, }, }; =20 @@ -2193,7 +2193,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2206,7 +2206,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2217,7 +2217,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2231,7 +2231,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, - .share_level =3D CPU_TOPO_LEVEL_DIE, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, }, }; =20 @@ -2247,7 +2247,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2260,7 +2260,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2271,7 +2271,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2285,7 +2285,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, - .share_level =3D CPU_TOPO_LEVEL_DIE, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, }, }; =20 @@ -2301,7 +2301,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2314,7 +2314,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2325,7 +2325,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2339,7 +2339,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, - .share_level =3D CPU_TOPO_LEVEL_DIE, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, }, }; =20 @@ -2355,7 +2355,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2368,7 +2368,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2379,7 +2379,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2393,7 +2393,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, - .share_level =3D CPU_TOPO_LEVEL_DIE, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, }, }; =20 @@ -2409,7 +2409,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2422,7 +2422,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2433,7 +2433,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .partitions =3D 1, .sets =3D 2048, .lines_per_tag =3D 1, - .share_level =3D CPU_TOPO_LEVEL_CORE, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2447,7 +2447,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, - .share_level =3D CPU_TOPO_LEVEL_DIE, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, }, }; =20 @@ -6591,7 +6591,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, =20 /* Share the cache at package level. */ *eax |=3D max_thread_ids_for_cache(&topo_info, - CPU_TOPO_LEVEL_PACKAGE) << 14; + CPU_TOPOLOGY_LEVEL_SOCKET) << 14; } } } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { @@ -8169,10 +8169,10 @@ static void x86_cpu_init_default_topo(X86CPU *cpu) env->nr_modules =3D 1; env->nr_dies =3D 1; =20 - /* SMT, core and package levels are set by default. */ - set_bit(CPU_TOPO_LEVEL_SMT, env->avail_cpu_topo); - set_bit(CPU_TOPO_LEVEL_CORE, env->avail_cpu_topo); - set_bit(CPU_TOPO_LEVEL_PACKAGE, env->avail_cpu_topo); + /* thread, core and socket levels are set by default. */ + set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); + set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); + set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); } =20 static void x86_cpu_initfn(Object *obj) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 59959b8b7a4d..00b23bc5d1f1 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1716,7 +1716,7 @@ typedef struct CPUCacheInfo { * Used to encode CPUID[4].EAX[bits 25:14] or * CPUID[0x8000001D].EAX[bits 25:14]. */ - enum CPUTopoLevel share_level; + CpuTopologyLevel share_level; } CPUCacheInfo; =20 =20 @@ -2051,7 +2051,7 @@ typedef struct CPUArchState { unsigned nr_modules; =20 /* Bitmap of available CPU topology levels for this CPU. */ - DECLARE_BITMAP(avail_cpu_topo, CPU_TOPO_LEVEL_MAX); + DECLARE_BITMAP(avail_cpu_topo, CPU_TOPOLOGY_LEVEL__MAX); } CPUX86State; =20 struct kvm_msrs; --=20 2.34.1 From nobody Thu Nov 14 07:18:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1730449085; cv=none; d=zohomail.com; s=zohoarc; b=FKoaMp4WxmXoaYwPjVXEEjwfxXq0z/OvWchl420eG0tEzD6XkCbBgZDMGQQ1hHT0laSu/ROdJJwX44ESTPLkcR6fNW6zkanc0wyMFF3YsrCNupZ81r3fD3PHixxgIGZZ3XDqr9UGnAamQOHkmmn6mpqkNfA3zfBYmbnUXu5n0fE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Cc: Yongwei Ma Subject: [PATCH v5 3/9] qapi/qom: Define cache enumeration and properties for machine Date: Fri, 1 Nov 2024 16:33:25 +0800 Message-Id: <20241101083331.340178-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101083331.340178-1-zhao1.liu@intel.com> References: <20241101083331.340178-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.366, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730449086402116600 Content-Type: text/plain; charset="utf-8" The x86 and ARM need to allow user to configure cache properties (current only topology): * For x86, the default cache topology model (of max/host CPU) does not always match the Host's real physical cache topology. Performance can increase when the configured virtual topology is closer to the physical topology than a default topology would be. * For ARM, QEMU can't get the cache topology information from the CPU registers, then user configuration is necessary. Additionally, the cache information is also needed for MPAM emulation (for TCG) to build the right PPTT. Define smp-cache related enumeration and properties in QAPI, so that user could configure cache properties for SMP system through -machine in the subsequent patch. Cache enumeration (CacheLevelAndType) is implemented as the combination of cache level (level 1/2/3) and cache type (data/instruction/unified). Currently, separated L1 cache (L1 data cache and L1 instruction cache) with unified higher-level cache (e.g., unified L2 and L3 caches), is the most common cache architectures. Therefore, enumerate the L1 D-cache, L1 I-cache, L2 cache and L3 cache with smp-cache object to add the basic cache topology support. Other kinds of caches (e.g., L1 unified or L2/L3 separated caches) can be added directly into CacheLevelAndType if necessary. Cache properties (SmpCacheProperties) currently only contains cache topology information, and other cache properties can be added in it if necessary. Note, define cache topology based on CPU topology level with two reasons: 1. In practice, a cache will always be bound to the CPU container (either private in the CPU container or shared among multiple containers), and CPU container is often expressed in terms of CPU topology level. 2. The x86's cache-related CPUIDs encode cache topology based on APIC ID's CPU topology layout. And the ACPI PPTT table that ARM/RISCV relies on also requires CPU containers to help indicate the private shared hierarchy of the cache. Therefore, for SMP systems, it is natural to use the CPU topology hierarchy directly in QEMU to define the cache topology. With smp-cache QAPI support, add smp cache topology for machine by parsing the smp-cache object list. Also add the helper to access/update cache topology level of machine. Suggested-by: Daniel P. Berrange Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Suggested by credit: * Referred to Daniel's suggestion to introduce cache object list. --- Changes since Patch v3: * Dropped "invalid" level check since now we don't enumerate it in QAPI. (Daniel) * Added a helper to update MachineState.smp_cache ( machine_set_cache_topo_level). --- hw/core/machine-smp.c | 37 +++++++++++++++++++++++++++++ hw/core/machine.c | 44 +++++++++++++++++++++++++++++++++++ include/hw/boards.h | 12 ++++++++++ qapi/machine-common.json | 50 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 143 insertions(+) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index 5d8d7edcbd3f..c6d90cd6d413 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -261,6 +261,31 @@ void machine_parse_smp_config(MachineState *ms, } } =20 +bool machine_parse_smp_cache(MachineState *ms, + const SmpCachePropertiesList *caches, + Error **errp) +{ + const SmpCachePropertiesList *node; + DECLARE_BITMAP(caches_bitmap, CACHE_LEVEL_AND_TYPE__MAX); + + for (node =3D caches; node; node =3D node->next) { + /* Prohibit users from repeating settings. */ + if (test_bit(node->value->cache, caches_bitmap)) { + error_setg(errp, + "Invalid cache properties: %s. " + "The cache properties are duplicated", + CacheLevelAndType_str(node->value->cache)); + return false; + } + + machine_set_cache_topo_level(ms, node->value->cache, + node->value->topology); + set_bit(node->value->cache, caches_bitmap); + } + + return true; +} + unsigned int machine_topo_get_cores_per_socket(const MachineState *ms) { return ms->smp.cores * ms->smp.modules * ms->smp.clusters * ms->smp.di= es; @@ -270,3 +295,15 @@ unsigned int machine_topo_get_threads_per_socket(const= MachineState *ms) { return ms->smp.threads * machine_topo_get_cores_per_socket(ms); } + +CpuTopologyLevel machine_get_cache_topo_level(const MachineState *ms, + CacheLevelAndType cache) +{ + return ms->smp_cache.props[cache].topology; +} + +void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cach= e, + CpuTopologyLevel level) +{ + ms->smp_cache.props[cache].topology =3D level; +} diff --git a/hw/core/machine.c b/hw/core/machine.c index 222799bc46e6..62aa3ad8a675 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -932,6 +932,40 @@ static void machine_set_smp(Object *obj, Visitor *v, c= onst char *name, machine_parse_smp_config(ms, config, errp); } =20 +static void machine_get_smp_cache(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + MachineState *ms =3D MACHINE(obj); + SmpCache *cache =3D &ms->smp_cache; + SmpCachePropertiesList *head =3D NULL; + SmpCachePropertiesList **tail =3D &head; + + for (int i =3D 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { + SmpCacheProperties *node =3D g_new(SmpCacheProperties, 1); + + node->cache =3D cache->props[i].cache; + node->topology =3D cache->props[i].topology; + QAPI_LIST_APPEND(tail, node); + } + + visit_type_SmpCachePropertiesList(v, name, &head, errp); + qapi_free_SmpCachePropertiesList(head); +} + +static void machine_set_smp_cache(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + MachineState *ms =3D MACHINE(obj); + SmpCachePropertiesList *caches; + + if (!visit_type_SmpCachePropertiesList(v, name, &caches, errp)) { + return; + } + + machine_parse_smp_cache(ms, caches, errp); + qapi_free_SmpCachePropertiesList(caches); +} + static void machine_get_boot(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -1092,6 +1126,11 @@ static void machine_class_init(ObjectClass *oc, void= *data) object_class_property_set_description(oc, "smp", "CPU topology"); =20 + object_class_property_add(oc, "smp-cache", "SmpCachePropertiesWrapper", + machine_get_smp_cache, machine_set_smp_cache, NULL, NULL); + object_class_property_set_description(oc, "smp-cache", + "Cache properties list for SMP machine"); + object_class_property_add(oc, "phandle-start", "int", machine_get_phandle_start, machine_set_phandle_start, NULL, NULL); @@ -1230,6 +1269,11 @@ static void machine_initfn(Object *obj) ms->smp.cores =3D 1; ms->smp.threads =3D 1; =20 + for (int i =3D 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { + ms->smp_cache.props[i].cache =3D (CacheLevelAndType)i; + ms->smp_cache.props[i].topology =3D CPU_TOPOLOGY_LEVEL_DEFAULT; + } + machine_copy_boot_config(ms, &(BootConfiguration){ 0 }); } =20 diff --git a/include/hw/boards.h b/include/hw/boards.h index 91f2edd3924b..f12a727b4008 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -44,8 +44,15 @@ void machine_set_cpu_numa_node(MachineState *machine, Error **errp); void machine_parse_smp_config(MachineState *ms, const SMPConfiguration *config, Error **errp= ); +bool machine_parse_smp_cache(MachineState *ms, + const SmpCachePropertiesList *caches, + Error **errp); unsigned int machine_topo_get_cores_per_socket(const MachineState *ms); unsigned int machine_topo_get_threads_per_socket(const MachineState *ms); +CpuTopologyLevel machine_get_cache_topo_level(const MachineState *ms, + CacheLevelAndType cache); +void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cach= e, + CpuTopologyLevel level); void machine_memory_devices_init(MachineState *ms, hwaddr base, uint64_t s= ize); =20 /** @@ -371,6 +378,10 @@ typedef struct CpuTopology { unsigned int max_cpus; } CpuTopology; =20 +typedef struct SmpCache { + SmpCacheProperties props[CACHE_LEVEL_AND_TYPE__MAX]; +} SmpCache; + /** * MachineState: */ @@ -421,6 +432,7 @@ struct MachineState { AccelState *accelerator; CPUArchIdList *possible_cpus; CpuTopology smp; + SmpCache smp_cache; struct NVDIMMState *nvdimms_state; struct NumaState *numa_state; }; diff --git a/qapi/machine-common.json b/qapi/machine-common.json index 1a5687fb99fc..298e51f373a3 100644 --- a/qapi/machine-common.json +++ b/qapi/machine-common.json @@ -60,3 +60,53 @@ { 'enum': 'CpuTopologyLevel', 'data': [ 'thread', 'core', 'module', 'cluster', 'die', 'socket', 'book', 'drawer', 'default' ] } + +## +# @CacheLevelAndType: +# +# Caches a system may have. The enumeration value here is the +# combination of cache level and cache type. +# +# @l1d: L1 data cache. +# +# @l1i: L1 instruction cache. +# +# @l2: L2 (unified) cache. +# +# @l3: L3 (unified) cache +# +# Since: 9.2 +## +{ 'enum': 'CacheLevelAndType', + 'data': [ 'l1d', 'l1i', 'l2', 'l3' ] } + +## +# @SmpCacheProperties: +# +# Cache information for SMP system. +# +# @cache: Cache name, which is the combination of cache level +# and cache type. +# +# @topology: Cache topology level. It accepts the CPU topology +# enumeration as the parameter, i.e., CPUs in the same +# topology container share the same cache. +# +# Since: 9.2 +## +{ 'struct': 'SmpCacheProperties', + 'data': { + 'cache': 'CacheLevelAndType', + 'topology': 'CpuTopologyLevel' } } + +## +# @SmpCachePropertiesWrapper: +# +# List wrapper of SmpCacheProperties. +# +# @caches: the list of SmpCacheProperties. +# +# Since 9.2 +## +{ 'struct': 'SmpCachePropertiesWrapper', + 'data': { 'caches': ['SmpCacheProperties'] } } --=20 2.34.1 From nobody Thu Nov 14 07:18:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1730449052; cv=none; d=zohomail.com; s=zohoarc; b=R5sOiWFoJ4LIbaP/Y3A15h3y+38spiMll5L4LM/KlnroXRMlg4qcC6+SHWl/R+U6WBLDCtBM5WnHlTh2793wfgWJduWZdaFNkmMBR0Uy5VhVVNjs/g4Nv+s0YhkuoBRdMQcMbkWFjKTfgGIBaYXRMvfQyLBVbDtfwF1/X3Ah1yY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730449052; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0iFY51lH1D0hyX3RZp+N+Kc+7Fdj3kVCkhSxBN80RyE=; b=lKXXwZ5O0s/d6MsJ74pPlMGXv4kz8UF4MPtSB2Rs5CbU5OESJCJM0r4ELbfadEvTXnyXR80egrHVNiRjwoFavnJTFOnHn3S4xXHA4R+0p8WH94xg51e3Dh03HDyhLvwSrQ331cFtI/M/KS34KyxytMiaalqa3uTe6Rf067Z7m4c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1730449052055536.1324565952922; Fri, 1 Nov 2024 01:17:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t6mpY-0004uq-O4; Fri, 01 Nov 2024 04:16:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6mpV-0004qy-3X; Fri, 01 Nov 2024 04:16:25 -0400 Received: from mgamail.intel.com ([192.198.163.16]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6mpT-0001QQ-Cr; Fri, 01 Nov 2024 04:16:24 -0400 Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2024 01:16:22 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa003.fm.intel.com with ESMTP; 01 Nov 2024 01:16:16 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730448984; x=1761984984; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E+zkEptv6x8nT44rXYHjEFJL+24l6aO0fCh+CMO/upA=; b=N+Djl/DYimZ5O7JZxRb0c6UzqNhkhm6Us2hXIEJgWUz5O8kJcbeO4dqb 56YVvyM8MFxNgA7g1xX9nYrdp8Hx2x5PR/nxC8K/NEwX+kgZAnZFT6wsO NurS9S6wLMl/hb8Pu9I2+agw8pOd141RZa/sB0C1bIywWVgZGztfYQIJz xMg4Ay44Xwv5wLR4DWAWv0//6YpFRRJ+U+Lv4TsAmn/KRD/KZCHpDeCUw XturGG0cw+BebTlgN2YBUsfkO+QT8DL0xR11fmWeAM7FAiCY94Zznao/w BCEFR6OrN1HDtY1TZO722qLTxYHKY5FivSPijWEvWj4S1h/iwUfHAkVyl A==; X-CSE-ConnectionGUID: dw+hTohTRm+9+A9SgBbz/A== X-CSE-MsgGUID: W7T+RrhzT2G0wuvAdh16aA== X-IronPort-AV: E=McAfee;i="6700,10204,11242"; a="17846045" X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="17846045" X-CSE-ConnectionGUID: lbUxUVPyRUaFO+h8PpQtzg== X-CSE-MsgGUID: j7+CQvoERvCthoCj5OUWJA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="86834611" From: Zhao Liu To: =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Cc: Yongwei Ma Subject: [PATCH v5 4/9] hw/core: Check smp cache topology support for machine Date: Fri, 1 Nov 2024 16:33:26 +0800 Message-Id: <20241101083331.340178-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101083331.340178-1-zhao1.liu@intel.com> References: <20241101083331.340178-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.366, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730449054490116600 Content-Type: text/plain; charset="utf-8" Add cache_supported flags in SMPCompatProps to allow machines to configure various caches support. And check the compatibility of the cache properties with the machine support in machine_parse_smp_cache(). Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Changes since Patch v3: * Dropped cache level check because if some fields is marked as default, then we can't guarentee the hierarchies are correct. (Daniel) --- hw/core/machine-smp.c | 41 +++++++++++++++++++++++++++++++++++++++++ include/hw/boards.h | 3 +++ 2 files changed, 44 insertions(+) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index c6d90cd6d413..ebb7a134a7be 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -261,10 +261,32 @@ void machine_parse_smp_config(MachineState *ms, } } =20 +static bool machine_check_topo_support(MachineState *ms, + CpuTopologyLevel topo, + Error **errp) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + + if ((topo =3D=3D CPU_TOPOLOGY_LEVEL_MODULE && !mc->smp_props.modules_s= upported) || + (topo =3D=3D CPU_TOPOLOGY_LEVEL_CLUSTER && !mc->smp_props.clusters= _supported) || + (topo =3D=3D CPU_TOPOLOGY_LEVEL_DIE && !mc->smp_props.dies_support= ed) || + (topo =3D=3D CPU_TOPOLOGY_LEVEL_BOOK && !mc->smp_props.books_suppo= rted) || + (topo =3D=3D CPU_TOPOLOGY_LEVEL_DRAWER && !mc->smp_props.drawers_s= upported)) { + error_setg(errp, + "Invalid topology level: %s. " + "The topology level is not supported by this machine", + CpuTopologyLevel_str(topo)); + return false; + } + + return true; +} + bool machine_parse_smp_cache(MachineState *ms, const SmpCachePropertiesList *caches, Error **errp) { + MachineClass *mc =3D MACHINE_GET_CLASS(ms); const SmpCachePropertiesList *node; DECLARE_BITMAP(caches_bitmap, CACHE_LEVEL_AND_TYPE__MAX); =20 @@ -283,6 +305,25 @@ bool machine_parse_smp_cache(MachineState *ms, set_bit(node->value->cache, caches_bitmap); } =20 + for (int i =3D 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { + const SmpCacheProperties *props =3D &ms->smp_cache.props[i]; + + /* + * Reject non "default" topology level if the cache isn't + * supported by the machine. + */ + if (props->topology !=3D CPU_TOPOLOGY_LEVEL_DEFAULT && + !mc->smp_props.cache_supported[props->cache]) { + error_setg(errp, + "%s cache topology not supported by this machine", + CacheLevelAndType_str(node->value->cache)); + return false; + } + + if (!machine_check_topo_support(ms, props->topology, errp)) { + return false; + } + } return true; } =20 diff --git a/include/hw/boards.h b/include/hw/boards.h index f12a727b4008..cda12070fc52 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -153,6 +153,8 @@ typedef struct { * @books_supported - whether books are supported by the machine * @drawers_supported - whether drawers are supported by the machine * @modules_supported - whether modules are supported by the machine + * @cache_supported - whether cache (l1d, l1i, l2 and l3) configuration are + * supported by the machine */ typedef struct { bool prefer_sockets; @@ -162,6 +164,7 @@ typedef struct { bool books_supported; bool drawers_supported; bool modules_supported; + bool cache_supported[CACHE_LEVEL_AND_TYPE__MAX]; } SMPCompatProps; =20 /** --=20 2.34.1 From nobody Thu Nov 14 07:18:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="86834620" From: Zhao Liu To: =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Subject: [PATCH v5 5/9] hw/core: Add a helper to check the cache topology level Date: Fri, 1 Nov 2024 16:33:27 +0800 Message-Id: <20241101083331.340178-6-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101083331.340178-1-zhao1.liu@intel.com> References: <20241101083331.340178-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.366, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730449054602116600 Content-Type: text/plain; charset="utf-8" Currently, we have no way to expose the arch-specific default cache model because the cache model is sometimes related to the CPU model (e.g., i386). Since the user might configure "default" level, any comparison with "default" is meaningless before the machine knows the specific level that "default" refers to. We can only check the correctness of the cache topology after the arch loads the user-configured cache model from MachineState.smp_cache and consumes the special "default" level by replacing it with the specific level. Signed-off-by: Zhao Liu Reviewed-by: Jonathan Cameron --- Changes since Patch v3: * New commit to make cache topology check as a separate helper, so that arch-specific code could use this helper to check cache topology. --- hw/core/machine-smp.c | 48 +++++++++++++++++++++++++++++++++++++++++++ include/hw/boards.h | 1 + 2 files changed, 49 insertions(+) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index ebb7a134a7be..640b2114b429 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -348,3 +348,51 @@ void machine_set_cache_topo_level(MachineState *ms, Ca= cheLevelAndType cache, { ms->smp_cache.props[cache].topology =3D level; } + +/* + * When both cache1 and cache2 are configured with specific topology levels + * (not default level), is cache1's topology level higher than cache2? + */ +static bool smp_cache_topo_cmp(const SmpCache *smp_cache, + CacheLevelAndType cache1, + CacheLevelAndType cache2) +{ + /* + * Before comparing, the "default" topology level should be replaced + * with the specific level. + */ + assert(smp_cache->props[cache1].topology !=3D CPU_TOPOLOGY_LEVEL_DEFAU= LT); + + return smp_cache->props[cache1].topology > smp_cache->props[cache2].to= pology; +} + +/* + * Currently, we have no way to expose the arch-specific default cache mod= el + * because the cache model is sometimes related to the CPU model (e.g., i3= 86). + * + * We can only check the correctness of the cache topology after the arch = loads + * the user-configured cache model from MachineState and consumes the spec= ial + * "default" level by replacing it with the specific level. + */ +bool machine_check_smp_cache(const MachineState *ms, Error **errp) +{ + if (smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L1D, + CACHE_LEVEL_AND_TYPE_L2) || + smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L1I, + CACHE_LEVEL_AND_TYPE_L2)) { + error_setg(errp, + "Invalid smp cache topology. " + "L2 cache topology level shouldn't be lower than L1 cac= he"); + return false; + } + + if (smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L2, + CACHE_LEVEL_AND_TYPE_L3)) { + error_setg(errp, + "Invalid smp cache topology. " + "L3 cache topology level shouldn't be lower than L2 cac= he"); + return false; + } + + return true; +} diff --git a/include/hw/boards.h b/include/hw/boards.h index cda12070fc52..e07fcf0983e1 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -53,6 +53,7 @@ CpuTopologyLevel machine_get_cache_topo_level(const Machi= neState *ms, CacheLevelAndType cache); void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cach= e, CpuTopologyLevel level); +bool machine_check_smp_cache(const MachineState *ms, Error **errp); void machine_memory_devices_init(MachineState *ms, hwaddr base, uint64_t s= ize); =20 /** --=20 2.34.1 From nobody Thu Nov 14 07:18:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1730449177; cv=none; d=zohomail.com; s=zohoarc; b=CRfIO2bB3rc8ZbAY2PZzCfURSs58kfQCcSBRBIiH0lEGNS5HmZdoQURwQUTQ4FjBxQ4F1RaiQgSoUdzCasVuWtWy4RJro6hz4WQdUs9QTYlJ7TH/+5IS5MfhIMgIEMhdg8lrgTK6rAWZCP/VBTBJgBKhqGjJ/bVPV2nWERBjETY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730449177; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gLW4V9jJ67HX16rkfMNSocK4BeExM6bMIdBZoNY2oZs=; b=hOM3FXo1P4g/5NIudYH4CGZp/iMS7izjZMCprRZQGLUlVg5HpCc7YINLiYTGdz+YqCQ75FaSq7A014LMX+AY4um4c0fdaWCH6IFde/l7xOTXwOqZA6r63gzSOdfERnTo7asCGp7oVSd4Jbr9NroWRj14vhbTuOt/OT0ScCcmy38= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1730449177944405.3895121212256; Fri, 1 Nov 2024 01:19:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t6mpi-00050M-Di; Fri, 01 Nov 2024 04:16:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6mpf-0004wM-N3; Fri, 01 Nov 2024 04:16:35 -0400 Received: from mgamail.intel.com ([192.198.163.16]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6mpe-0001QQ-7Q; Fri, 01 Nov 2024 04:16:35 -0400 Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2024 01:16:33 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa003.fm.intel.com with ESMTP; 01 Nov 2024 01:16:27 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730448994; x=1761984994; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EGbj8vANOciytGjaNrt6k0e5IUuBc6pcu0CAwcWWiBE=; b=Xn0Z5HmHZmzKGptnD4FB02ElbLYOgR71kbdqzDoK4Xdxpr4KmMLO9MdF MTc9ziYzVb/Masd8LwJ4GNRxZadov45yf92r+mx6f6gyCh+galJKTXc/p fzP6KqOuD6G5Ea8Otvm1mM6pd/1D012tzdD/uWQBTxbHzGTawaOob9X3t /9c7IC7/fXxlNaxYayZimGQwevZGnBbTbVKVKRNsBw08nzbLWNiSCIQwe KR+jUh+StrPhCiAkbr3y1siXDcj3EwaeQYpGIyS0Y8BITDikSsxWd8gJQ NzMdQ/7FCy35i3I4Wq7wRS7Mx9ZXu3kBeez/rOGcsU4ZotfG6Sl0tWYvL w==; X-CSE-ConnectionGUID: bR0dLzSWQ4aGHc949+OMkA== X-CSE-MsgGUID: 30Mn9tcUQkGMA1o1InSa8A== X-IronPort-AV: E=McAfee;i="6700,10204,11242"; a="17846068" X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="17846068" X-CSE-ConnectionGUID: dcN29vuBQH2Be9GsJjYitw== X-CSE-MsgGUID: uZqiM3dqRvOYw1MHcf0HIQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="86834642" From: Zhao Liu To: =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Cc: Yongwei Ma Subject: [PATCH v5 6/9] i386/cpu: Support thread and module level cache topology Date: Fri, 1 Nov 2024 16:33:28 +0800 Message-Id: <20241101083331.340178-7-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101083331.340178-1-zhao1.liu@intel.com> References: <20241101083331.340178-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.366, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730449178554116600 Content-Type: text/plain; charset="utf-8" Allow cache to be defined at the thread and module level. This increases flexibility for x86 users to customize their cache topology. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- target/i386/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d46710a4030f..09aaed95a856 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -243,9 +243,15 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInf= o *topo_info, uint32_t num_ids =3D 0; =20 switch (share_level) { + case CPU_TOPOLOGY_LEVEL_THREAD: + num_ids =3D 1; + break; case CPU_TOPOLOGY_LEVEL_CORE: num_ids =3D 1 << apicid_core_offset(topo_info); break; + case CPU_TOPOLOGY_LEVEL_MODULE: + num_ids =3D 1 << apicid_module_offset(topo_info); + break; case CPU_TOPOLOGY_LEVEL_DIE: num_ids =3D 1 << apicid_die_offset(topo_info); break; @@ -253,10 +259,6 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInf= o *topo_info, num_ids =3D 1 << apicid_pkg_offset(topo_info); break; default: - /* - * Currently there is no use case for THREAD and MODULE, so use - * assert directly to facilitate debugging. - */ g_assert_not_reached(); } =20 --=20 2.34.1 From nobody Thu Nov 14 07:18:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1730449066; cv=none; d=zohomail.com; s=zohoarc; b=hOQhruDr46n1MbpMdggqCjrQ8orAH+g+ZbQrU/GsqNm5eMLyetD253+sBNP0jyY3XFdu0BovU+iIH1PCYqHJZnbQa3+xEXp5kX5MdPhr/EYafFcJ2/GFXTHesekNoWOAWF5xSoqoYU5IqRuWaseSJWVYJJV9yHkrxhXiRj/7vL0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730449066; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qviPWeR044cXdS5udTXsEKPmpBKES18daBHsN4CzlEo=; b=PpXI1MpE1RjuNkPxQo+UAIyabOKLOlY7EFpZfHuU3eUJ1ggsidM3kYxxBOaWmJnx5SMsRoc9MGS6R6a/Sr6EJ4hHdNePtfFgpBnWAEM0DaErF60Kwa5tS2oG1N4mWxzWB4KIVvCKSZFikB0rAU6beWUMNSPsWimKhag7UoKH+0Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1730449066961903.7566033099287; Fri, 1 Nov 2024 01:17:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t6mpw-0005DX-Vd; Fri, 01 Nov 2024 04:16:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6mpl-00057A-Au; Fri, 01 Nov 2024 04:16:41 -0400 Received: from mgamail.intel.com ([192.198.163.16]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6mpj-0001QQ-K4; Fri, 01 Nov 2024 04:16:41 -0400 Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2024 01:16:38 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa003.fm.intel.com with ESMTP; 01 Nov 2024 01:16:33 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730449000; x=1761985000; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bCnGCo7lhItXTGaZkRo+zcrebUj+4UEX/OLY4d7GGMM=; b=FobMbu4Xukni446pNBuNVq1zamC+r/Snoqbwyt/K4reaxODwK43XrR4E kB1eoChzqEVd8lhrdby4qxJek2KPgEp5Cpfw/8qCPRzaHd+lvFYXsQqiw yMGqv2Ke6Blw6dYU6yavtEz/4XlNFlFqtU+tvBOGlZHAf/+JdlkX1J5ki iRB9b4caIyLs0mmvKHoFEPHqOKGuC45Y8/LoHOfP05SdkWUGbGs6WcM2N v9KagM3A7oE3j8uMruL/WNhZzV+IOQiIHnR0lQQypcu+G6npGDr7KvlfB gBSgbbGGjJcbXmO5dkoPnXWoIVVIUYERNQC9USTnVeItD7U8e6KK+l125 A==; X-CSE-ConnectionGUID: DjnV6ChiQg20D6PcXHt0lw== X-CSE-MsgGUID: 6jroPtkeT4SO6BwkTnMNhw== X-IronPort-AV: E=McAfee;i="6700,10204,11242"; a="17846079" X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="17846079" X-CSE-ConnectionGUID: UjbTBaHpTeWvuNuNrNxO0w== X-CSE-MsgGUID: wPlBlOj8Sd6HAXnmqU/Jng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="86834675" From: Zhao Liu To: =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Cc: Yongwei Ma Subject: [PATCH v5 7/9] i386/cpu: Update cache topology with machine's configuration Date: Fri, 1 Nov 2024 16:33:29 +0800 Message-Id: <20241101083331.340178-8-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101083331.340178-1-zhao1.liu@intel.com> References: <20241101083331.340178-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.366, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730449068267116600 Content-Type: text/plain; charset="utf-8" User will configure smp cache topology via -machine smp-cache. For this case, update the x86 CPUs' cache topology with user's configuration in MachineState. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Changes since Patch v3: * Updated MachineState.smp_cache to consume "default" level and did a check to ensure topological hierarchical relationships are correct. --- target/i386/cpu.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 09aaed95a856..1cf4cda1e647 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7753,6 +7753,64 @@ static void x86_cpu_hyperv_realize(X86CPU *cpu) cpu->hyperv_limits[2] =3D 0; } =20 +#ifndef CONFIG_USER_ONLY +static bool x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu, + Error **errp) +{ + CPUX86State *env =3D &cpu->env; + CpuTopologyLevel level; + + level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D); + if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l1d_cache->share_level =3D level; + env->cache_info_amd.l1d_cache->share_level =3D level; + } else { + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, + env->cache_info_cpuid4.l1d_cache->share_level); + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, + env->cache_info_amd.l1d_cache->share_level); + } + + level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I); + if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l1i_cache->share_level =3D level; + env->cache_info_amd.l1i_cache->share_level =3D level; + } else { + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, + env->cache_info_cpuid4.l1i_cache->share_level); + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, + env->cache_info_amd.l1i_cache->share_level); + } + + level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2); + if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l2_cache->share_level =3D level; + env->cache_info_amd.l2_cache->share_level =3D level; + } else { + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, + env->cache_info_cpuid4.l2_cache->share_level); + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, + env->cache_info_amd.l2_cache->share_level); + } + + level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3); + if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l3_cache->share_level =3D level; + env->cache_info_amd.l3_cache->share_level =3D level; + } else { + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, + env->cache_info_cpuid4.l3_cache->share_level); + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, + env->cache_info_amd.l3_cache->share_level); + } + + if (!machine_check_smp_cache(ms, errp)) { + return false; + } + return true; +} +#endif + static void x86_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -7977,6 +8035,15 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) =20 #ifndef CONFIG_USER_ONLY MachineState *ms =3D MACHINE(qdev_get_machine()); + + /* + * TODO: Add a SMPCompatProps.has_caches flag to avoid useless updates + * if user didn't set smp_cache. + */ + if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { + return; + } + qemu_register_reset(x86_cpu_machine_reset_cb, cpu); =20 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { --=20 2.34.1 From nobody Thu Nov 14 07:18:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1730449190; cv=none; d=zohomail.com; s=zohoarc; b=hZgGFAYNwQ2j4qtE14AuZwlrgyEajULfCgNY/XHJiMMHCHV/vEo4I/VpEyJ4VcmFO68bWKJBcnrYjJzkLxIiyS//6HqGWoBxGGdf63wcRromFjNq98eInz+4pqdU41ZXu+16fVXEPee6PXEgMT5r8hZ3tjft+QD5QdrGnQwkNzA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730449190; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: x5ZXqQLSSc2x4Q0A2tKsjQ== X-CSE-MsgGUID: aoucjMg6ShChM3IFIwYKuQ== X-IronPort-AV: E=McAfee;i="6700,10204,11242"; a="17846091" X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="17846091" X-CSE-ConnectionGUID: zrHITGPaQaSKU2H21ONDUg== X-CSE-MsgGUID: NfCN/3W3RXSTpoIvp8AN+A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="86834717" From: Zhao Liu To: =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Cc: Yongwei Ma Subject: [PATCH v5 8/9] i386/pc: Support cache topology in -machine for PC machine Date: Fri, 1 Nov 2024 16:33:30 +0800 Message-Id: <20241101083331.340178-9-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101083331.340178-1-zhao1.liu@intel.com> References: <20241101083331.340178-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.366, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730449190619116600 Content-Type: text/plain; charset="utf-8" Allow user to configure l1d, l1i, l2 and l3 cache topologies for PC machine. Additionally, add the document of "-machine smp-cache" in qemu-options.hx. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Changes since Patch v3: * Described the omitting cache will use "default" level and described the default cache topology model of i386 PC machine. (Daniel) --- hw/i386/pc.c | 4 ++++ qemu-options.hx | 31 ++++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2047633e4cf7..8aea2308dcb9 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1791,6 +1791,10 @@ static void pc_machine_class_init(ObjectClass *oc, v= oid *data) mc->nvdimm_supported =3D true; mc->smp_props.dies_supported =3D true; mc->smp_props.modules_supported =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] =3D true; mc->default_ram_id =3D "pc.ram"; pcmc->default_smbios_ep_type =3D SMBIOS_ENTRY_POINT_TYPE_AUTO; =20 diff --git a/qemu-options.hx b/qemu-options.hx index dacc9790a4b8..a18ed4a9a853 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -39,7 +39,8 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \ " memory-encryption=3D@var{} memory encryption object t= o use (default=3Dnone)\n" " hmat=3Don|off controls ACPI HMAT support (default=3Do= ff)\n" " memory-backend=3D'backend-id' specifies explicitly pr= ovided backend for main RAM (default=3Dnone)\n" - " cxl-fmw.0.targets.0=3Dfirsttarget,cxl-fmw.0.targets.1= =3Dsecondtarget,cxl-fmw.0.size=3Dsize[,cxl-fmw.0.interleave-granularity=3Dg= ranularity]\n", + " cxl-fmw.0.targets.0=3Dfirsttarget,cxl-fmw.0.targets.1= =3Dsecondtarget,cxl-fmw.0.size=3Dsize[,cxl-fmw.0.interleave-granularity=3Dg= ranularity]\n" + " smp-cache.0.cache=3Dcachename,smp-cache.0.topology=3D= topologylevel\n", QEMU_ARCH_ALL) SRST ``-machine [type=3D]name[,prop=3Dvalue[,...]]`` @@ -159,6 +160,34 @@ SRST :: =20 -machine cxl-fmw.0.targets.0=3Dcxl.0,cxl-fmw.0.targets.1=3Dcxl= .1,cxl-fmw.0.size=3D128G,cxl-fmw.0.interleave-granularity=3D512 + + ``smp-cache.0.cache=3Dcachename,smp-cache.0.topology=3Dtopologylevel`` + Define cache properties for SMP system. + + ``cache=3Dcachename`` specifies the cache that the properties will= be + applied on. This field is the combination of cache level and cache + type. It supports ``l1d`` (L1 data cache), ``l1i`` (L1 instruction + cache), ``l2`` (L2 unified cache) and ``l3`` (L3 unified cache). + + ``topology=3Dtopologylevel`` sets the cache topology level. It acc= epts + CPU topology levels including ``thread``, ``core``, ``module``, + ``cluster``, ``die``, ``socket``, ``book``, ``drawer`` and a speci= al + value ``default``. If ``default`` is set, then the cache topology = will + follow the architecture's default cache topology model. If another + topology level is set, the cache will be shared at corresponding C= PU + topology level. For example, ``topology=3Dcore`` makes the cache s= hared + by all threads within a core. The omitting cache will default to u= sing + the ``default`` level. + + The default cache topology model for an i386 PC machine is as foll= ows: + ``l1d``, ``l1i``, and ``l2`` caches are per ``core``, while the ``= l3`` + cache is per ``die``. + + Example: + + :: + + -machine smp-cache.0.cache=3Dl1d,smp-cache.0.topology=3Dcore,s= mp-cache.1.cache=3Dl1i,smp-cache.1.topology=3Dcore ERST =20 DEF("M", HAS_ARG, QEMU_OPTION_M, --=20 2.34.1 From nobody Thu Nov 14 07:18:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1730449122; cv=none; d=zohomail.com; s=zohoarc; b=DrAYSPV63MQH4JbiAv9N2tM1iFtL6iWfrzd/GF7yMdjyMsutO8KZTPH9vxERr7rlSsc5QZTgfg6NTtlRsLfBYmhcQ5S0xcp4LxDTkdvNwWs0RgAjCTjXX9gy9la9N2fQZzdFoVh7/akBuNMNSfmeY1m1ujKI2TJ2GjMRgakEaHQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730449122; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=dlnSKUGbAVnScE0hipLS5rVF9YVnuqQjBOa3jo8SatU=; b=GOHqRLXqaCdeU/cHCBQ4+lAYu+Qms2v3D2E707tiWGbwkR62ixhDhMCTljba1criHIYmzkQYeVqscZD11cRkWzv6ShRaL1A/mnGbXiup25jWVBrwioo3uu2A94QdZljKvM4UXNptfs3dVCJLsMoZ/AynlAC7E0qhkoapNWtkJSY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 173044912275618.27274313904752; Fri, 1 Nov 2024 01:18:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t6mq6-0005M4-KZ; Fri, 01 Nov 2024 04:17:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6mpx-0005ES-SW; Fri, 01 Nov 2024 04:16:55 -0400 Received: from mgamail.intel.com ([192.198.163.16]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6mpv-0001QQ-Cd; Fri, 01 Nov 2024 04:16:53 -0400 Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2024 01:16:50 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa003.fm.intel.com with ESMTP; 01 Nov 2024 01:16:44 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730449012; x=1761985012; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=se3A3A+kRvSwSAobc6tYFr7xeZZ8F/aVOqRAc4gXB10=; b=Oa73xaNgroSTh1S7dtucn+tBrDrlq2Remih3sbObqveh0bRThRnCcOL7 V5MWsxv36ngUVGOT9KCiA/ywzqXyhQtptXCSCYhKRfaKN5AWCH02ANGBA LC/NBORbMOpHg/lAkAb+MxCC4TFT/V4jJR3ibLlbo0ZCEPBtl9aF2RHzB csxR57jfqBK9MOmjOtNjAuZWt8HvKeELlsiVK6Lx0BUqjB3G4iV17/YXh DD4ASPkvZEGlYOtFyy8mx7hx4g8U5zoOIj5DecaCAsfQ0JIh8JAz5EAzd msYcTkcnmMWP4N0bJfofmhZ7Zczd+gqhqJXivgy8CG1IrVAWQErnIo/Aq A==; X-CSE-ConnectionGUID: vzOm0RRcTf2ZBncbIotCYw== X-CSE-MsgGUID: W5ac+AcgQ3iLv0JmK5AF/A== X-IronPort-AV: E=McAfee;i="6700,10204,11242"; a="17846103" X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="17846103" X-CSE-ConnectionGUID: MfnoaelzSjKKq1CkEaOG1g== X-CSE-MsgGUID: DHNWzy+0SfuGlV9pH5NKow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="86834736" From: Zhao Liu To: =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Subject: [PATCH v5 9/9] i386/cpu: add has_caches flag to check smp_cache configuration Date: Fri, 1 Nov 2024 16:33:31 +0800 Message-Id: <20241101083331.340178-10-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101083331.340178-1-zhao1.liu@intel.com> References: <20241101083331.340178-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.366, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730449124531116600 Content-Type: text/plain; charset="utf-8" From: Alireza Sanaee Add has_caches flag to SMPCompatProps, which helps in avoiding extra checks for every single layer of caches in x86 (and ARM in future). Signed-off-by: Alireza Sanaee Signed-off-by: Zhao Liu Reviewed-by: Jonathan Cameron --- Note: Picked from Alireza's series with the changes: * Moved the flag to SMPCompatProps with a new name "has_caches". This way, it remains consistent with the function and style of "has_clusters" in SMPCompatProps. * Dropped my previous TODO with the new flag. --- Changes since Patch v2: * Picked a new patch frome Alireza's ARM smp-cache series. --- hw/core/machine-smp.c | 2 ++ include/hw/boards.h | 3 +++ target/i386/cpu.c | 11 +++++------ 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index 640b2114b429..6ae7c4765402 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -324,6 +324,8 @@ bool machine_parse_smp_cache(MachineState *ms, return false; } } + + mc->smp_props.has_caches =3D true; return true; } =20 diff --git a/include/hw/boards.h b/include/hw/boards.h index e07fcf0983e1..2d650bbf13c4 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -156,6 +156,8 @@ typedef struct { * @modules_supported - whether modules are supported by the machine * @cache_supported - whether cache (l1d, l1i, l2 and l3) configuration are * supported by the machine + * @has_caches - whether cache properties are explicitly specified in the + * user provided smp-cache configuration */ typedef struct { bool prefer_sockets; @@ -166,6 +168,7 @@ typedef struct { bool drawers_supported; bool modules_supported; bool cache_supported[CACHE_LEVEL_AND_TYPE__MAX]; + bool has_caches; } SMPCompatProps; =20 /** diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1cf4cda1e647..49f19f896197 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8035,13 +8035,12 @@ static void x86_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 #ifndef CONFIG_USER_ONLY MachineState *ms =3D MACHINE(qdev_get_machine()); + MachineClass *mc =3D MACHINE_GET_CLASS(ms); =20 - /* - * TODO: Add a SMPCompatProps.has_caches flag to avoid useless updates - * if user didn't set smp_cache. - */ - if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { - return; + if (mc->smp_props.has_caches) { + if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { + return; + } } =20 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); --=20 2.34.1