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a="55492690" X-IronPort-AV: E=Sophos;i="6.11,247,1725346800"; d="scan'208";a="55492690" X-CSE-ConnectionGUID: jKS2wT4RSF6CcFtUll5oDQ== X-CSE-MsgGUID: JnXFS98bSpegqxc+I5avAQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,247,1725346800"; d="scan'208";a="82489528" From: Tao Su To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, zhao1.liu@intel.com, xuelian.guo@intel.com, tao1.su@linux.intel.com Subject: [PATCH v3 5/8] target/i386: add CPUID.24 features for AVX10 Date: Thu, 31 Oct 2024 16:52:30 +0800 Message-Id: <20241031085233.425388-6-tao1.su@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241031085233.425388-1-tao1.su@linux.intel.com> References: <20241031085233.425388-1-tao1.su@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.198.163.7; envelope-from=tao1.su@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -46 X-Spam_score: -4.7 X-Spam_bar: ---- X-Spam_report: (-4.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.366, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730365169578116600 Content-Type: text/plain; charset="utf-8" Introduce features for the supported vector bit lengths. Signed-off-by: Tao Su Link: https://lore.kernel.org/r/20241028024512.156724-3-tao1.su@linux.intel= .com Link: https://lore.kernel.org/r/20241028024512.156724-4-tao1.su@linux.intel= .com Signed-off-by: Paolo Bonzini Reviewed-by: Zhao Liu Tested-by: Xuelian Guo --- target/i386/cpu.c | 15 +++++++++++++++ target/i386/cpu.h | 8 ++++++++ 2 files changed, 23 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 284ff062df..762c69d0b9 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -901,6 +901,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendo= r1, #define TCG_SGX_12_0_EAX_FEATURES 0 #define TCG_SGX_12_0_EBX_FEATURES 0 #define TCG_SGX_12_1_EAX_FEATURES 0 +#define TCG_24_0_EBX_FEATURES 0 =20 #if defined CONFIG_USER_ONLY #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ @@ -1166,6 +1167,20 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D= { }, .tcg_features =3D TCG_7_2_EDX_FEATURES, }, + [FEAT_24_0_EBX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + [16] =3D "avx10-128", + [17] =3D "avx10-256", + [18] =3D "avx10-512", + }, + .cpuid =3D { + .eax =3D 0x24, + .needs_ecx =3D true, .ecx =3D 0, + .reg =3D R_EBX, + }, + .tcg_features =3D TCG_24_0_EBX_FEATURES, + }, [FEAT_8000_0007_EDX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d845384dcd..5566a13f4f 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -662,6 +662,7 @@ typedef enum FeatureWord { FEAT_XSAVE_XSS_HI, /* CPUID[EAX=3D0xd,ECX=3D1].EDX */ FEAT_7_1_EDX, /* CPUID[EAX=3D7,ECX=3D1].EDX */ FEAT_7_2_EDX, /* CPUID[EAX=3D7,ECX=3D2].EDX */ + FEAT_24_0_EBX, /* CPUID[EAX=3D0x24,ECX=3D0].EBX */ FEATURE_WORDS, } FeatureWord; =20 @@ -990,6 +991,13 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cp= u, FeatureWord w); /* Packets which contain IP payload have LIP values */ #define CPUID_14_0_ECX_LIP (1U << 31) =20 +/* AVX10 128-bit vector support is present */ +#define CPUID_24_0_EBX_AVX10_128 (1U << 16) +/* AVX10 256-bit vector support is present */ +#define CPUID_24_0_EBX_AVX10_256 (1U << 17) +/* AVX10 512-bit vector support is present */ +#define CPUID_24_0_EBX_AVX10_512 (1U << 18) + /* RAS Features */ #define CPUID_8000_0007_EBX_OVERFLOW_RECOV (1U << 0) #define CPUID_8000_0007_EBX_SUCCOR (1U << 1) --=20 2.34.1