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Wed, 30 Oct 2024 21:22:13 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Markovic , Faraz Shahbazker , Aleksandar Rakic , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 02/14] target/mips: Enable MSA ASE for mips32r6-generic Date: Thu, 31 Oct 2024 01:21:18 -0300 Message-ID: <20241031042130.98450-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241031042130.98450-1-philmd@linaro.org> References: <20241031042130.98450-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=philmd@linaro.org; helo=mail-lf1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730348563780116600 From: Aleksandar Markovic Enable MSA ASE for mips32r6-generic CPU. Signed-off-by: Aleksandar Markovic Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic Reviewed-by: Aleksandar Rikalo Message-ID: Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu-defs.c.inc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index fbf787d8ce1..1ab026c57e7 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -478,14 +478,15 @@ const mips_def_t mips_defs[] =3D (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA)= | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 =3D MIPS_CONFIG2, - .CP0_Config3 =3D MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) | + .CP0_Config3 =3D MIPS_CONFIG3 | (1 << CP0C3_MSAP) | + (1 << CP0C3_BP) | (1 << CP0C3_BI) | (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1U << CP0C3_M), .CP0_Config4 =3D MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | (3 << CP0C4_IE) | (1U << CP0C4_M), .CP0_Config5 =3D MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB= ), - .CP0_Config5_rw_bitmask =3D (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | - (1 << CP0C5_UFE), + .CP0_Config5_rw_bitmask =3D (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) | + (1 << CP0C5_FRE) | (1 << CP0C5_SBRI), .CP0_LLAddr_rw_bitmask =3D 0, .CP0_LLAddr_shift =3D 0, .SYNCI_Step =3D 32, @@ -499,6 +500,7 @@ const mips_def_t mips_defs[] =3D (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV= ), .CP1_fcr31 =3D (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), .CP1_fcr31_rw_bitmask =3D 0x0103FFFF, + .MSAIR =3D 0x03 << MSAIR_ProcID, .SEGBITS =3D 32, .PABITS =3D 32, .insn_flags =3D CPU_MIPS32R6 | ASE_MICROMIPS, --=20 2.45.2