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Wed, 30 Oct 2024 21:24:41 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 12/14] target/mips: Introduce ase_3d_available() helper Date: Thu, 31 Oct 2024 01:21:28 -0300 Message-ID: <20241031042130.98450-13-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241031042130.98450-1-philmd@linaro.org> References: <20241031042130.98450-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=philmd@linaro.org; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730348698378116600 Determine if the MIPS-3D ASE is implemented by checking the state of the 3D bit in the FIR CP1 control register. Remove the then unused ASE_MIPS3D definition. Note, this allows using MIPS-3D on the mips64dspr2 model. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20241021145832.34920-1-philmd@linaro.org> --- target/mips/cpu.h | 6 ++++++ target/mips/mips-defs.h | 1 - target/mips/tcg/translate.c | 8 ++++++-- target/mips/cpu-defs.c.inc | 4 ++-- target/mips/tcg/micromips_translate.c.inc | 5 ++++- 5 files changed, 18 insertions(+), 6 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index a4a46ebbe98..3dbfbfdb3d3 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1319,6 +1319,12 @@ bool cpu_type_supports_cps_smp(const char *cpu_type); bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); =20 +/* Check presence of MIPS-3D ASE */ +static inline bool ase_3d_available(const CPUMIPSState *env) +{ + return env->active_fpu.fcr0 & (1 << FCR0_3D); +} + /* Check presence of MSA implementation */ static inline bool ase_msa_available(CPUMIPSState *env) { diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index a6cebe0265c..6b5cd0d8f53 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -26,7 +26,6 @@ * bits 24-39: MIPS ASEs */ #define ASE_MIPS16 0x0000000001000000ULL -#define ASE_MIPS3D 0x0000000002000000ULL #define ASE_MDMX 0x0000000004000000ULL #define ASE_DSP 0x0000000008000000ULL #define ASE_DSP_R2 0x0000000010000000ULL diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 2d01f5c4a8b..9a3ae10a919 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -14710,7 +14710,9 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) } else { /* OPC_BC1ANY2 */ check_cop1x(ctx); - check_insn(ctx, ASE_MIPS3D); + if (!ase_3d_available(env)) { + return false; + } gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), (rt >> 2) & 0x7, imm << 2); } @@ -14725,7 +14727,9 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) check_cp1_enabled(ctx); check_insn_opc_removed(ctx, ISA_MIPS_R6); check_cop1x(ctx); - check_insn(ctx, ASE_MIPS3D); + if (!ase_3d_available(env)) { + return false; + } /* fall through */ case OPC_BC1: check_cp1_enabled(ctx); diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 1ab026c57e7..09bd62d430a 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -663,7 +663,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 40, .PABITS =3D 36, - .insn_flags =3D CPU_MIPS64R1 | ASE_MIPS3D, + .insn_flags =3D CPU_MIPS64R1, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -692,7 +692,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 42, .PABITS =3D 36, - .insn_flags =3D CPU_MIPS64R2 | ASE_MIPS3D, + .insn_flags =3D CPU_MIPS64R2, .mmu_type =3D MMU_TYPE_R4000, }, { diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/mi= cromips_translate.c.inc index 3cbf53bf2b3..c479bec1081 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -2484,7 +2484,10 @@ static void decode_micromips32_opc(CPUMIPSState *env= , DisasContext *ctx) mips32_op =3D OPC_BC1TANY4; do_cp1mips3d: check_cop1x(ctx); - check_insn(ctx, ASE_MIPS3D); + if (!ase_3d_available(env)) { + gen_reserved_instruction(ctx); + break; + } /* Fall through */ do_cp1branch: if (env->CP0_Config1 & (1 << CP0C1_FP)) { --=20 2.45.2