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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21105707064sm3022795ad.70.2024.10.30.20.53.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Oct 2024 20:53:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730346825; x=1730951625; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=i8Ikw2NcsgZpzTmcdbGYuA7GcCItNURSpq5TPRbUd/s=; b=AYEH3vg7x+YF/28pVjmrARmqcw8pdbWXQxlZxTtZ1OEfmON8sqvJ+Ui3wVxTBip+Vk fsEl7sbDZtoKT+r+aCz30j8wk2SjK1fMra8f3gumxo//EXAkN0gLUGdmbFTFB3UG+xWe bX1I7h4z/qqHzmJxziXBEd0cEmGnyUS43WqkWrw6kSkVqswwzpWsPh+MIlQi+9phSYAf qxWIYpAdfeL/KD85G0IIPAk+PpqXAlGhDY1/Fu7sQH5sjYpieFqg/o3YH4zmTeGdicGr Uewl5RZSNaFAcufXgcxH3HdjwRn8bK58MpbVOLQlRT1mIFot3aCrt8bCsPzYBoVxoMiG 2u5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730346825; x=1730951625; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i8Ikw2NcsgZpzTmcdbGYuA7GcCItNURSpq5TPRbUd/s=; b=G9BzP6N/1Y+El0QB84KbNBwBcPmSnuzAN6JQCnqK5e+vN4VcjeHuXMWodii+pesC9Y dB9FyrG+8PC0c4I6mCQUNB+z3TBXAPgqoP5YjLo4DxTAJDS2jyqm9lkoJi38uurkkdSY hcLCAmrU74TlPEln5+TkncNrfc3Bp5BoedFsIJr+UzyXYE/dUUk/TC4u7SId1Y4kOVT/ ABZU5o8auYLdVgR1zNY3IX2Y4GGJJAkZ7ZKmCAUMnf0RRC6ug4Hpo/j3Avou+UyioXN5 /W8uSz5PLP9iJuBUPyars0rSXb82bJ5JWZQ5L4VdoYmY4DYKsKz/P9PCWfU6xggcshPI sjlQ== X-Gm-Message-State: AOJu0YyLeEO+gBlM9GZFLy+eYrYXk8LRkOTPMbx+4ITE8q0Kn97NHhUv XJ9u0MwA5jOVKfUAEt3KfqMMQTVT0fnDxo3Xg4fss+jkVoJpcsNv79kIpYDv X-Google-Smtp-Source: AGHT+IHFPwHe2b10sA90Ce0axRItyk/2Jvz0H5iVMUl98Tvz+xt3/ttku0z3tq6/MDTye3zr66ZQrQ== X-Received: by 2002:a17:902:ce07:b0:205:709e:1949 with SMTP id d9443c01a7336-21103cc0a4emr18540615ad.57.1730346824762; Wed, 30 Oct 2024 20:53:44 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, TANG Tiancheng , Liu Zhiwei , Alistair Francis Subject: [PULL 06/50] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU Date: Thu, 31 Oct 2024 13:52:34 +1000 Message-ID: <20241031035319.731906-7-alistair.francis@wdc.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241031035319.731906-1-alistair.francis@wdc.com> References: <20241031035319.731906-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1730346866344116600 Content-Type: text/plain; charset="utf-8" From: TANG Tiancheng Ensure mcause high bit is correctly set by using 32-bit width for RV32 mode and 64-bit width for RV64 mode. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis Message-ID: <20240919055048.562-6-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 621bf4c1b8..203c0a92ab 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1677,6 +1677,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong tinst =3D 0; target_ulong htval =3D 0; target_ulong mtval2 =3D 0; + int sxlen =3D 0; + int mxlen =3D 0; =20 if (!async) { /* set tval to badaddr for traps with address information */ @@ -1805,7 +1807,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) s =3D set_field(s, MSTATUS_SPP, env->priv); s =3D set_field(s, MSTATUS_SIE, 0); env->mstatus =3D s; - env->scause =3D cause | ((target_ulong)async << (TARGET_LONG_BITS = - 1)); + sxlen =3D 16 << riscv_cpu_sxl(env); + env->scause =3D cause | ((target_ulong)async << (sxlen - 1)); env->sepc =3D env->pc; env->stval =3D tval; env->htval =3D htval; @@ -1836,7 +1839,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) s =3D set_field(s, MSTATUS_MPP, env->priv); s =3D set_field(s, MSTATUS_MIE, 0); env->mstatus =3D s; - env->mcause =3D cause | ~(((target_ulong)-1) >> async); + mxlen =3D 16 << riscv_cpu_mxl(env); + env->mcause =3D cause | ((target_ulong)async << (mxlen - 1)); env->mepc =3D env->pc; env->mtval =3D tval; env->mtval2 =3D mtval2; --=20 2.47.0