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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21105707064sm3022795ad.70.2024.10.30.20.53.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Oct 2024 20:53:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730346813; x=1730951613; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8jPqU1u91/bvSwOR04NsIfK/88xElvIo76xw8RLdAv8=; b=e0iji0sjVpozJdg0BJv3FySJMS/SZ0bLiveP7ebSfrQ1xOYqb/eFKCMEcaZ1Bj6QZq Prb4qVMstP7U7FMFQcy228nnT8CKZD1qZS6Zz+nYTW4TqMhjJVlTI9bt5bS6m5cDfCxc 3U8tb+HT0J+YphNS3loL95RHouRzLGo8GXHwrWtwMiAaxOaaqsdmcrKVEsOk8Rt3kc1H eWlWHB8QUlFCqdfUGwNkxGmtl6spjEnCOT1nCyBpjxN619teAgLptHSeTEaUXpvvyij/ 7Fu2h7/sCmFwK9pZj/CVgRxDhl+h+ksbDWAiBQwtNBPGM0lFYWI6fWScsDsBsbAVY+Hy dMsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730346813; x=1730951613; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8jPqU1u91/bvSwOR04NsIfK/88xElvIo76xw8RLdAv8=; b=PJDvdEE6O0cQu/yJb35PWxrOUYWBUDhfSte2kn+euiUoFGMh76SKYMEqHm6bMKs4Ib hw3wmQKGX4wuqtgfWsJkjDy8kz6TxCmE57ymgJ3gGef+mFsv7MJVC+KE1qPIcceYqOax iIwaWZWTSkTAJSIWpkc4rI7jHy4T8D28BEiotyALG+q9qhBQ8IVR3uOggAXP5NIGnq4s uzcFAOwVDGv/I/W//yOXbB/xpZ0aKc7vGdFbNRmskfLDw8R5dSQKY85AE5DRAFupjeoh CQY/ouqhD0sJFJgP3DNInsfgOKsBOxI5BWcsJDDXASQEYFjl+7Tj2zN0IohlxZrf+pqn rzLg== X-Gm-Message-State: AOJu0Yy2at+er+AIeUQrfa6OR2q238TZ/0+nsCa1AVCbCJUDufW+S4O1 pI4VvQh9beDnKWWNOH1mdPFD25EX+c2iFGbki/e/leA47sNg7TvkRU76+hlg X-Google-Smtp-Source: AGHT+IGOWhtrvQPRuv5QLFl/4FLuqI3Kbqlm+xazclLMOotKFwq4iF2Db/lWCXarVNKpp8/xVPSN4g== X-Received: by 2002:a17:902:d4c6:b0:20c:d2d9:765c with SMTP id d9443c01a7336-21103acd304mr25343285ad.15.1730346812780; Wed, 30 Oct 2024 20:53:32 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, TANG Tiancheng , Liu Zhiwei , Alistair Francis Subject: [PULL 02/50] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI Date: Thu, 31 Oct 2024 13:52:30 +1000 Message-ID: <20241031035319.731906-3-alistair.francis@wdc.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241031035319.731906-1-alistair.francis@wdc.com> References: <20241031035319.731906-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1730346866433116600 Content-Type: text/plain; charset="utf-8" From: TANG Tiancheng RV32 OpenSBI need a fw_dynamic_info parameter with 32-bit fields instead of target_ulong. In RV64 QEMU, target_ulong is 64. So it is not right for booting RV32 OpenS= BI. We create a fw_dynmaic_info32 struct for this purpose. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis Message-ID: <20240919055048.562-2-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis --- include/hw/riscv/boot.h | 4 +++- include/hw/riscv/boot_opensbi.h | 29 +++++++++++++++++++++++++++ hw/riscv/boot.c | 35 ++++++++++++++++++++++----------- hw/riscv/sifive_u.c | 3 ++- 4 files changed, 57 insertions(+), 14 deletions(-) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 18bfe9f7bf..f778b560de 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -56,7 +56,9 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RIS= CVHartArrayState *harts hwaddr rom_base, hwaddr rom_size, uint64_t kernel_entry, uint64_t fdt_load_addr); -void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, +void riscv_rom_copy_firmware_info(MachineState *machine, + RISCVHartArrayState *harts, + hwaddr rom_base, hwaddr rom_size, uint32_t reset_vec_size, uint64_t kernel_entry); diff --git a/include/hw/riscv/boot_opensbi.h b/include/hw/riscv/boot_opensb= i.h index 1b749663dc..18664a174b 100644 --- a/include/hw/riscv/boot_opensbi.h +++ b/include/hw/riscv/boot_opensbi.h @@ -58,4 +58,33 @@ struct fw_dynamic_info { target_long boot_hart; }; =20 +/** Representation dynamic info passed by previous booting stage */ +struct fw_dynamic_info32 { + /** Info magic */ + int32_t magic; + /** Info version */ + int32_t version; + /** Next booting stage address */ + int32_t next_addr; + /** Next booting stage mode */ + int32_t next_mode; + /** Options for OpenSBI library */ + int32_t options; + /** + * Preferred boot HART id + * + * It is possible that the previous booting stage uses same link + * address as the FW_DYNAMIC firmware. In this case, the relocation + * lottery mechanism can potentially overwrite the previous booting + * stage while other HARTs are still running in the previous booting + * stage leading to boot-time crash. To avoid this boot-time crash, + * the previous booting stage can specify last HART that will jump + * to the FW_DYNAMIC firmware as the preferred boot HART. + * + * To avoid specifying a preferred boot HART, the previous booting + * stage can set it to -1UL which will force the FW_DYNAMIC firmware + * to use the relocation lottery mechanism. + */ + int32_t boot_hart; +}; #endif diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 9115ecd91f..2e319168db 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -343,27 +343,33 @@ void riscv_load_fdt(hwaddr fdt_addr, void *fdt) rom_ptr_for_as(&address_space_memory, fdt_addr, fd= tsize)); } =20 -void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, - hwaddr rom_size, uint32_t reset_vec_size, +void riscv_rom_copy_firmware_info(MachineState *machine, + RISCVHartArrayState *harts, + hwaddr rom_base, hwaddr rom_size, + uint32_t reset_vec_size, uint64_t kernel_entry) { + struct fw_dynamic_info32 dinfo32; struct fw_dynamic_info dinfo; size_t dinfo_len; =20 - if (sizeof(dinfo.magic) =3D=3D 4) { - dinfo.magic =3D cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); - dinfo.version =3D cpu_to_le32(FW_DYNAMIC_INFO_VERSION); - dinfo.next_mode =3D cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); - dinfo.next_addr =3D cpu_to_le32(kernel_entry); + if (riscv_is_32bit(harts)) { + dinfo32.magic =3D cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); + dinfo32.version =3D cpu_to_le32(FW_DYNAMIC_INFO_VERSION); + dinfo32.next_mode =3D cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); + dinfo32.next_addr =3D cpu_to_le32(kernel_entry); + dinfo32.options =3D 0; + dinfo32.boot_hart =3D 0; + dinfo_len =3D sizeof(dinfo32); } else { dinfo.magic =3D cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); dinfo.version =3D cpu_to_le64(FW_DYNAMIC_INFO_VERSION); dinfo.next_mode =3D cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); dinfo.next_addr =3D cpu_to_le64(kernel_entry); + dinfo.options =3D 0; + dinfo.boot_hart =3D 0; + dinfo_len =3D sizeof(dinfo); } - dinfo.options =3D 0; - dinfo.boot_hart =3D 0; - dinfo_len =3D sizeof(dinfo); =20 /** * copy the dynamic firmware info. This information is specific to @@ -375,7 +381,10 @@ void riscv_rom_copy_firmware_info(MachineState *machin= e, hwaddr rom_base, exit(1); } =20 - rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len, + rom_add_blob_fixed_as("mrom.finfo", + riscv_is_32bit(harts) ? + (void *)&dinfo32 : (void *)&dinfo, + dinfo_len, rom_base + reset_vec_size, &address_space_memory); } @@ -431,7 +440,9 @@ void riscv_setup_rom_reset_vec(MachineState *machine, R= ISCVHartArrayState *harts } rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), rom_base, &address_space_memory); - riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset= _vec), + riscv_rom_copy_firmware_info(machine, harts, + rom_base, rom_size, + sizeof(reset_vec), kernel_entry); } =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9b3dcf3a7a..c5e74126b1 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -645,7 +645,8 @@ static void sifive_u_machine_init(MachineState *machine) rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), memmap[SIFIVE_U_DEV_MROM].base, &address_space_m= emory); =20 - riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base, + riscv_rom_copy_firmware_info(machine, &s->soc.u_cpus, + memmap[SIFIVE_U_DEV_MROM].base, memmap[SIFIVE_U_DEV_MROM].size, sizeof(reset_vec), kernel_entry); =20 --=20 2.47.0