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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21105707064sm3022795ad.70.2024.10.30.20.54.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Oct 2024 20:54:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730346872; x=1730951672; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XbZ/LjJfFs/QHKQ1e2MgBXUAGXwqum8xGgpfZ3IOsvA=; b=So/9UAXxZOSuWlqk+OKtTOwND2bGAT9IyPjaCq/5LYmCvbLjXQ9P2lRmJ2ZwPH9De6 Fp0GUClYxzRXrlz8I1b0gzkps1MvFazevF52ZwbK2vMrBh/O1CAoxrbFokWmtYDOdgGl TXp7N5kQZfCv0TKA+hCPMSTPmb+vdP307eEea+4jF+bHtBpnoFE5eOaHXjqC2t3UfrM/ LbWp2c4CP3nqkHmGy00BceiLRWT6XRn2ir0eV9/nqZV7v63SU3FAlRkyVYfkSYPyIuXM NooO4Mn+0x5KLYC/nr/inef/GFCgsTqlVxe0n+ZoePnL4ArCaZ8jeYrvoIabawgJD7Bu U5fA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730346872; x=1730951672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XbZ/LjJfFs/QHKQ1e2MgBXUAGXwqum8xGgpfZ3IOsvA=; b=jsUh1PWJd8FTNGHIg3FCmdWVUFVNjT+M5IyvsXYjg0SRmDYpiVy3Yi3TTnNSGOlj4X vsiIHNZxJjqh0CCXsA8Ue4Ov79vmkFpSLNleAW4ccEP5J5Iz4OqYkeZ0doFH/5xtqkj0 j98qtRRa8j027zBqszEC4wt0Nvw3Xn22NYvQ9XMNGWWTU+CkALu37PEIxdVgqeo6Pua/ g50OGFi4G3Ur+KAmpvAJ824DbwpU3QdKC+euAQYJ25tM9fZ4z1R/M2ikGhgIzwE1OTuJ FBNvGygx2dPPNop4X6bRyCVZgG4RuiQ7FlQm3kt0xkDP6Bd9kyS0TJUiMaoPrj17TGDW qpBA== X-Gm-Message-State: AOJu0YwjSI0J/JcISaSUF6y6mZ60ubPAv0Jwf2NaAJnZca+0c4o5Butc CvVbKvQnUSHG/z53nk8zkSu449WqssmoCMEgTGGJ8scfp5KQe+VAha8cD8Vg X-Google-Smtp-Source: AGHT+IFH7FC4tIlxMtck7WZ541JjZ+rzDnW0NQ40GMLBZW+HDQZESORSt2oXMcGwsQxC4yIA7lhqBQ== X-Received: by 2002:a17:903:41cf:b0:20b:51b0:4b22 with SMTP id d9443c01a7336-210c6c8f84fmr217162495ad.47.1730346871990; Wed, 30 Oct 2024 20:54:31 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Deepak Gupta , Jim Shu , Andy Chiu , Richard Henderson , Alistair Francis Subject: [PULL 21/50] target/riscv: tracking indirect branches (fcfi) for zicfilp Date: Thu, 31 Oct 2024 13:52:49 +1000 Message-ID: <20241031035319.731906-22-alistair.francis@wdc.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241031035319.731906-1-alistair.francis@wdc.com> References: <20241031035319.731906-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=alistair23@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1730347044800116600 Content-Type: text/plain; charset="utf-8" From: Deepak Gupta zicfilp protects forward control flow (if enabled) by enforcing all indirect call and jmp must land on a landing pad instruction `lpad`. If target of an indirect call or jmp is not `lpad` then cpu/hart must raise a sw check exception with tval =3D 2. This patch implements the mechanism using TCG. Target architecture branch instruction must define the end of a TB. Using this property, during translation of branch instruction, TB flag =3D FCFI_LP_EXPECTED can be set. Translation of target TB can check if FCFI_LP_EXPECTED flag is set and a flag (fcfi_lp_expected) can be set in DisasContext. If `lpad` gets translated, fcfi_lp_expected flag in DisasContext can be cleared. Else it'll fault. Signed-off-by: Deepak Gupta Co-developed-by: Jim Shu Co-developed-by: Andy Chiu Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-ID: <20241008225010.1861630-7-debug@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 +++ target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_helper.c | 10 ++++++++++ target/riscv/translate.c | 23 +++++++++++++++++++++++ 4 files changed, 39 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 67ce6e0a03..c3a03f878b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -622,6 +622,9 @@ FIELD(TB_FLAGS, ITRIGGER, 22, 1) FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) FIELD(TB_FLAGS, PRIV, 24, 2) FIELD(TB_FLAGS, AXL, 26, 2) +/* zicfilp needs a TB flag to track indirect branches */ +FIELD(TB_FLAGS, FCFI_ENABLED, 28, 1) +FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 29, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8df6043ef1..e7387c9b8f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -692,6 +692,9 @@ typedef enum RISCVException { RISCV_EXCP_SEMIHOST =3D 0x3f, } RISCVException; =20 +/* zicfilp defines lp violation results in sw check with tval =3D 2*/ +#define RISCV_EXCP_SW_CHECK_FCFI_TVAL 2 + #define RISCV_EXCP_INT_FLAG 0x80000000 #define RISCV_EXCP_INT_MASK 0x7fffffff =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index fa4982e940..6a63c37083 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -132,6 +132,16 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *p= c, flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); } =20 + if (cpu_get_fcfien(env)) { + /* + * For Forward CFI, only the expectation of a lpad at + * the start of the block is tracked via env->elp. env->elp + * is turned on during jalr translation. + */ + flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, env->elp); + flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_ENABLED, 1); + } + #ifdef CONFIG_USER_ONLY fs =3D EXT_STATUS_DIRTY; vs =3D EXT_STATUS_DIRTY; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index acba90f170..b5c0511b4b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -116,6 +116,9 @@ typedef struct DisasContext { bool frm_valid; bool insn_start_updated; const GPtrArray *decoders; + /* zicfilp extension. fcfi_enabled, lp expected or not */ + bool fcfi_enabled; + bool fcfi_lp_expected; } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -1238,6 +1241,8 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->pm_base_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLE= D); ctx->ztso =3D cpu->cfg.ext_ztso; ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); + ctx->fcfi_lp_expected =3D FIELD_EX32(tb_flags, TB_FLAGS, FCFI_LP_EXPEC= TED); + ctx->fcfi_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, FCFI_ENABLED); ctx->zero =3D tcg_constant_tl(0); ctx->virt_inst_excp =3D false; ctx->decoders =3D cpu->decoders; @@ -1270,6 +1275,24 @@ static void riscv_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) decode_opc(env, ctx, opcode16); ctx->base.pc_next +=3D ctx->cur_insn_len; =20 + /* + * If 'fcfi_lp_expected' is still true after processing the instructio= n, + * then we did not see an 'lpad' instruction, and must raise an except= ion. + * Insert code to raise the exception at the start of the insn; any ot= her + * code the insn may have emitted will be deleted as dead code followi= ng + * the noreturn exception + */ + if (ctx->fcfi_lp_expected) { + /* Emit after insn_start, i.e. before the op following insn_start.= */ + tcg_ctx->emit_before_op =3D QTAILQ_NEXT(ctx->base.insn_start, link= ); + tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), + tcg_env, offsetof(CPURISCVState, sw_check_code)); + gen_helper_raise_exception(tcg_env, + tcg_constant_i32(RISCV_EXCP_SW_CHECK)); + tcg_ctx->emit_before_op =3D NULL; + ctx->base.is_jmp =3D DISAS_NORETURN; + } + /* Only the first insn within a TB is allowed to cross a page boundary= . */ if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next))= { --=20 2.47.0