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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21105707064sm3022795ad.70.2024.10.30.20.54.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Oct 2024 20:54:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730346862; x=1730951662; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6kQzrMfXF4jNckFUkc1Y8TzwHOUGgNTCayNN/f/ZzX4=; b=TEVQoIQqFHXOybHTzQBaQoh+GKjtot97pchCK629WZJ0/E9yv6dKeFiVcUsszysLdB VEk1puztkYcP/LD/0liVw4q7SFPDbuDf2/84+z7hE2Nnzr/KEWJLeBhu7RdiKuXjDBds vvsKWWVjK+naEp9aTdEkxUGQdfbYb9uX+BCMJ37/8m8NOE1c/b+yKe/FT47rkSpvlWxM 7nWLVHamuJCeZuJ14CJtWcJ1MejE91Yo8ScLw1fPm1Kb/113tFs6xDEkb7mlcvF1qTrC RKOWTqSkEG+a+SN41Tq6XSPTYetoLzxX/CQu+HSMCHHEhKI3a0BzQuF0a7VPoEZiOm4z pvuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730346862; x=1730951662; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6kQzrMfXF4jNckFUkc1Y8TzwHOUGgNTCayNN/f/ZzX4=; b=Kv831RVP1hpCZhUctPZBiIf8w8DsC0rjrfYb7bHPe1QZnUiTTwIKJZ9T/F0xaRA8HV omVlDOCfX5wguGdyANHSLC3Z3GZ/pYu0ZB1BDiykihWRyFGQmHp5Gov06Ogan+ND13fu T5KnS64qHJhbDOTpn1XrIf9y1Z1ra2SvEGnBhW0oGnAKhoNEzdCqwnE30Z049zVfB0FY YOWO8NCG8YjZ+GDU1qpAOHXdB/s3eeVhQuicDSl7DHZk8AeUs5VRM19JWq7MRtAcu/V6 ex3OsHRhKzUtPFK1ayN4hw2v3XDDD8mG5HBR3snknCOAH+uNYjUpGOpi/+3DBUYufsIX PwBA== X-Gm-Message-State: AOJu0Yz6M2ROk/HmzYJRnL7r8SvlawEq6U8c9H8zVVj2DrdZQvbSMXv7 n1hmBncg031DHXnADbZlZ6bqBvp33d9DfQiNBKadxz2CrT0PcU9clkSV+pYP X-Google-Smtp-Source: AGHT+IFi3NnjDa0WoHzvycgQu5bpFlajfdmOEB7bHqjaKwIl8XQBz1MhAtLLbPZklmbDniO/W9T99g== X-Received: by 2002:a17:903:943:b0:205:68a4:b2d8 with SMTP id d9443c01a7336-21103aaa063mr25102975ad.11.1730346861743; Wed, 30 Oct 2024 20:54:21 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Deepak Gupta , Jim Shu , Andy Chiu , Richard Henderson , Alistair Francis Subject: [PULL 18/50] target/riscv: Introduce elp state and enabling controls for zicfilp Date: Thu, 31 Oct 2024 13:52:46 +1000 Message-ID: <20241031035319.731906-19-alistair.francis@wdc.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241031035319.731906-1-alistair.francis@wdc.com> References: <20241031035319.731906-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1730346876245116600 Content-Type: text/plain; charset="utf-8" From: Deepak Gupta zicfilp introduces a new state elp ("expected landing pad") in cpu. During normal execution, elp is idle (NO_LP_EXPECTED) i.e not expecting landing pad. On an indirect call, elp moves LP_EXPECTED. When elp is LP_EXPECTED, only a subsquent landing pad instruction can set state back to NO_LP_EXPECTED. On reset, elp is set to NO_LP_EXPECTED. zicfilp is enabled via bit2 in *envcfg CSRs. Enabling control for M-mode is in mseccfg CSR at bit position 10. On trap, elp state is saved away in *status. Adds elp to the migration state as well. Signed-off-by: Deepak Gupta Co-developed-by: Jim Shu Co-developed-by: Andy Chiu Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-ID: <20241008225010.1861630-4-debug@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 6 ++++++ target/riscv/pmp.h | 3 ++- target/riscv/cpu.c | 3 +++ target/riscv/csr.c | 31 +++++++++++++++++++++++++++++++ target/riscv/machine.c | 19 +++++++++++++++++++ target/riscv/pmp.c | 5 +++++ 7 files changed, 68 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b7b082833d..d68cb6e9e0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -230,6 +230,8 @@ struct CPUArchState { =20 target_ulong jvt; =20 + /* elp state for zicfilp extension */ + bool elp; #ifdef CONFIG_USER_ONLY uint32_t elf_flags; #endif diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7e3f629356..8df6043ef1 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -552,6 +552,8 @@ #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ #define MSTATUS_TW 0x00200000 /* since: priv-1.10 */ #define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ +#define MSTATUS_SPELP 0x00800000 /* zicfilp */ +#define MSTATUS_MPELP 0x020000000000 /* zicfilp */ #define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL =20 @@ -582,6 +584,7 @@ typedef enum { #define SSTATUS_XS 0x00018000 #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ #define SSTATUS_MXR 0x00080000 +#define SSTATUS_SPELP MSTATUS_SPELP /* zicfilp */ =20 #define SSTATUS64_UXL 0x0000000300000000ULL =20 @@ -754,6 +757,7 @@ typedef enum RISCVException { =20 /* Execution environment configuration bits */ #define MENVCFG_FIOM BIT(0) +#define MENVCFG_LPE BIT(2) /* zicfilp */ #define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) @@ -767,11 +771,13 @@ typedef enum RISCVException { #define MENVCFGH_STCE BIT(31) =20 #define SENVCFG_FIOM MENVCFG_FIOM +#define SENVCFG_LPE MENVCFG_LPE #define SENVCFG_CBIE MENVCFG_CBIE #define SENVCFG_CBCFE MENVCFG_CBCFE #define SENVCFG_CBZE MENVCFG_CBZE =20 #define HENVCFG_FIOM MENVCFG_FIOM +#define HENVCFG_LPE MENVCFG_LPE #define HENVCFG_CBIE MENVCFG_CBIE #define HENVCFG_CBCFE MENVCFG_CBCFE #define HENVCFG_CBZE MENVCFG_CBZE diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index f5c10ce85c..e0530a17a3 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -44,7 +44,8 @@ typedef enum { MSECCFG_MMWP =3D 1 << 1, MSECCFG_RLB =3D 1 << 2, MSECCFG_USEED =3D 1 << 8, - MSECCFG_SSEED =3D 1 << 9 + MSECCFG_SSEED =3D 1 << 9, + MSECCFG_MLPE =3D 1 << 10, } mseccfg_field_t; =20 typedef struct { diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6fa2689f35..27fbbd11b9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1011,6 +1011,9 @@ static void riscv_cpu_reset_hold(Object *obj, ResetTy= pe type) env->menvcfg =3D 0; #endif =20 + /* on reset elp is clear */ + env->elp =3D false; + env->xl =3D riscv_cpu_mxl(env); riscv_cpu_update_mask(env); cs->exception_index =3D RISCV_EXCP_NONE; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c88ee1265e..02bcb8a23a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1598,6 +1598,11 @@ static RISCVException write_mstatus(CPURISCVState *e= nv, int csrno, } } =20 + /* If cfi lp extension is available, then apply cfi lp mask */ + if (env_archcpu(env)->cfg.ext_zicfilp) { + mask |=3D (MSTATUS_MPELP | MSTATUS_SPELP); + } + mstatus =3D (mstatus & ~mask) | (val & mask); =20 env->mstatus =3D mstatus; @@ -2344,6 +2349,10 @@ static RISCVException write_menvcfg(CPURISCVState *e= nv, int csrno, mask |=3D (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | (cfg->ext_svadu ? MENVCFG_ADUE : 0); + + if (env_archcpu(env)->cfg.ext_zicfilp) { + mask |=3D MENVCFG_LPE; + } } env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); =20 @@ -2396,6 +2405,10 @@ static RISCVException write_senvcfg(CPURISCVState *e= nv, int csrno, return ret; } =20 + if (env_archcpu(env)->cfg.ext_zicfilp) { + mask |=3D SENVCFG_LPE; + } + env->senvcfg =3D (env->senvcfg & ~mask) | (val & mask); return RISCV_EXCP_NONE; } @@ -2433,6 +2446,10 @@ static RISCVException write_henvcfg(CPURISCVState *e= nv, int csrno, =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { mask |=3D env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_A= DUE); + + if (env_archcpu(env)->cfg.ext_zicfilp) { + mask |=3D HENVCFG_LPE; + } } =20 env->henvcfg =3D (env->henvcfg & ~mask) | (val & mask); @@ -2897,6 +2914,10 @@ static RISCVException read_sstatus_i128(CPURISCVStat= e *env, int csrno, mask |=3D SSTATUS64_UXL; } =20 + if (env_archcpu(env)->cfg.ext_zicfilp) { + mask |=3D SSTATUS_SPELP; + } + *val =3D int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus)); return RISCV_EXCP_NONE; } @@ -2908,6 +2929,11 @@ static RISCVException read_sstatus(CPURISCVState *en= v, int csrno, if (env->xl !=3D MXL_RV32 || env->debugger) { mask |=3D SSTATUS64_UXL; } + + if (env_archcpu(env)->cfg.ext_zicfilp) { + mask |=3D SSTATUS_SPELP; + } + /* TODO: Use SXL not MXL. */ *val =3D add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); return RISCV_EXCP_NONE; @@ -2923,6 +2949,11 @@ static RISCVException write_sstatus(CPURISCVState *e= nv, int csrno, mask |=3D SSTATUS64_UXL; } } + + if (env_archcpu(env)->cfg.ext_zicfilp) { + mask |=3D SSTATUS_SPELP; + } + target_ulong newval =3D (env->mstatus & ~mask) | (val & mask); return write_mstatus(env, CSR_MSTATUS, newval); } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 492c2c6d9d..c3a06c288d 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -350,6 +350,24 @@ static const VMStateDescription vmstate_jvt =3D { } }; =20 +static bool elp_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + + return cpu->cfg.ext_zicfilp; +} + +static const VMStateDescription vmstate_elp =3D { + .name =3D "cpu/elp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D elp_needed, + .fields =3D (const VMStateField[]) { + VMSTATE_BOOL(env.elp, RISCVCPU), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", .version_id =3D 10, @@ -422,6 +440,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { &vmstate_debug, &vmstate_smstateen, &vmstate_jvt, + &vmstate_elp, NULL } }; diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 5e74b7220f..a1b36664fc 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -598,6 +598,11 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulon= g val) val &=3D ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB); } =20 + /* M-mode forward cfi to be enabled if cfi extension is implemented */ + if (env_archcpu(env)->cfg.ext_zicfilp) { + val |=3D (val & MSECCFG_MLPE); + } + env->mseccfg =3D val; } =20 --=20 2.47.0