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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21105707064sm3022795ad.70.2024.10.30.20.54.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Oct 2024 20:54:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730346855; x=1730951655; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HvHndEIaR1hHXVQ49EQ5dLHaTlYB46mZYAbDe9hCdeQ=; b=GzYGZMT4iQd3IgFlGWxGIFUo3rg7wdLI0wioF2oaLHsZXz/paQQSEokKRpMLCEDLU+ c6cATtsZ2WBxTgFqwcHmNlrTAtoguIdB6Hb6nZuJTSUtOG6mEq7aew/wVPR9yxiKM8c2 XTAamSNGwy8J81m5rU4ccjreQbUsc93OQmf/TXVTr2MmFZOm3s3JkFzU1FexkyiYzs1B 6nZC4yBE04GU4MV7TtoY3iwNhUl2O70KhkxQJoIn1TA5VlFWLNAQTsOnv3tAXshtm+3C EB9jpkXREnK5x9onloUwqum0ufPbcmh2D2QaR3XlsMWg/E6MDN6zEPoJub3nBeetbBxE mp4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730346855; x=1730951655; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HvHndEIaR1hHXVQ49EQ5dLHaTlYB46mZYAbDe9hCdeQ=; b=gvQKTlHvPovcIf8DEMXEaWrSaIgeXtPbFfAYl7l54KZx3Ceeml04ByQFH3UjgjIyqQ XxUdOHmMp8YvsGXzFuTcJ0mfkp/RLssnAna+2FaueJkcEooZi095wrT9GyyW4ToSkNmL +7x4wW3uZisREITxYMpGBBV9G/sLGtQ13qn38N5i91Glyiq5VJ9uH0llxvPZOJbpDwz0 cwEmOV7BEeORV4CJTTRSeAopg+W+hgvyjoz4TT6Qyor3A/Vvkiqnkz43brZs4iy9Yx7Q kPnr/AK1qLWaDNgtKXSb6zEQ+1u+brelUZ1UFG8zbOymfTD+D6+GkFqoKcuNNkeBYAZS 8XLw== X-Gm-Message-State: AOJu0Yyk7oHUVdCOsaYw4HnaaSnuBr+Z7RjWKWwN7mh1EHTlw11x4Mnd hIcGqdNXIF/V8NJ1MIORc/8PaN7Utyz5uGSHEBrkxd0HWlvWxjBJTRh4YVdE X-Google-Smtp-Source: AGHT+IF8vguwJRn/S/5S9k7HIqfjJ2ev9JGySXmzlJdP724znFQcnZnIZmbnppDgIKezE5ePOJ45CQ== X-Received: by 2002:a17:903:41ce:b0:20c:9821:69b6 with SMTP id d9443c01a7336-210c6ca1ba9mr238892585ad.58.1730346854836; Wed, 30 Oct 2024 20:54:14 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Deepak Gupta , Richard Henderson , Alistair Francis Subject: [PULL 16/50] target/riscv: expose *envcfg csr and priv to qemu-user as well Date: Thu, 31 Oct 2024 13:52:44 +1000 Message-ID: <20241031035319.731906-17-alistair.francis@wdc.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241031035319.731906-1-alistair.francis@wdc.com> References: <20241031035319.731906-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1730347312252116600 Content-Type: text/plain; charset="utf-8" From: Deepak Gupta Execution environment config CSR controlling user env and current privilege state shouldn't be limited to qemu-system only. *envcfg CSRs control enabling of features in next lesser mode. In some cases bits *envcfg CSR can be lit up by kernel as part of kernel policy or software (user app) can choose to opt-in by issuing a system call (e.g. prctl). In case of qemu-user, it should be no different because qemu is providing underlying execution environment facility and thus either should provide some default value in *envcfg CSRs or react to system calls (prctls) initiated from application. priv is set to PRV_U and menvcfg/senvcfg set to 0 for qemu-user on reest. `henvcfg` has been left for qemu-system only because it is not expected that someone will use qemu-user where application is expected to have hypervisor underneath which is controlling its execution environment. If such a need arises then `henvcfg` could be exposed as well. Relevant discussion: https://lore.kernel.org/all/CAKmqyKOTVWPFep2msTQVdUmJErkH+bqCcKEQ4hAnyDFPdW= Ke0Q@mail.gmail.com/ Signed-off-by: Deepak Gupta Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-ID: <20241008225010.1861630-2-debug@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 9 +++++---- target/riscv/cpu.c | 5 +++++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a63a29744c..b7b082833d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -234,8 +234,12 @@ struct CPUArchState { uint32_t elf_flags; #endif =20 -#ifndef CONFIG_USER_ONLY target_ulong priv; + /* CSRs for execution environment configuration */ + uint64_t menvcfg; + target_ulong senvcfg; + +#ifndef CONFIG_USER_ONLY /* This contains QEMU specific information about the virt state. */ bool virt_enabled; target_ulong geilen; @@ -445,12 +449,9 @@ struct CPUArchState { target_ulong upmmask; target_ulong upmbase; =20 - /* CSRs for execution environment configuration */ - uint64_t menvcfg; uint64_t mstateen[SMSTATEEN_MAX_COUNT]; uint64_t hstateen[SMSTATEEN_MAX_COUNT]; uint64_t sstateen[SMSTATEEN_MAX_COUNT]; - target_ulong senvcfg; uint64_t henvcfg; #endif target_ulong cur_pmmask; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2a78cd639b..f0e32c4e6e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1004,7 +1004,12 @@ static void riscv_cpu_reset_hold(Object *obj, ResetT= ype type) } =20 pmp_unlock_entries(env); +#else + env->priv =3D PRV_U; + env->senvcfg =3D 0; + env->menvcfg =3D 0; #endif + env->xl =3D riscv_cpu_mxl(env); riscv_cpu_update_mask(env); cs->exception_index =3D RISCV_EXCP_NONE; --=20 2.47.0