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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21105707064sm3022795ad.70.2024.10.30.20.53.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Oct 2024 20:54:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730346842; x=1730951642; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zkMM+SpFMUglcfQaluT/IwK1QZ7oQxstOZNmSOLZ8cc=; b=coJLaFGVd4pJHIKu7+YTZbwr4099XHQIVh+x8fCMj6iNnsurAapQO4g/MomxFPK9mc e9JdZNqI41l+9vK91sRrrUS6B68V0hG6FN4VuFR5JaGA4QF68QIvT/ry6zEozoMuCE6S fQ54d3dgBZ4Ui7mxZnv3c2oY/WkGyyhEOe4KJ3CXMddmc2IyDLFHKH8ODXEHSYkOWhBe Dz+abLyJFO0LU3g2F2rmQgvcy1IiBAwY7wSXK0D6nVybFkDNF77YzQO9iWZdw2oAyv31 jB2qqR1lR496yR2IP/DBm9eBW7FoWk4n1hpHIlrRIjcolrFdy+cfdhSczHWDaLY6yvpd mBzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730346842; x=1730951642; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zkMM+SpFMUglcfQaluT/IwK1QZ7oQxstOZNmSOLZ8cc=; b=sApzUqjcW0H8cEEws6aheepPNxrLOQriW7QekvgMGzB08FW160BDtXAAgtwpL7RJ7i rzOH8dxgjAdkkB5R1al/0i9K0Sj13txQABCMkpSC/ntLN8atESFPoYiTFh7YC2AE7mCe q3ZCigRNk62L5t+UwZkBPk3RTuLAEOn+XvroAQdvmrDpT351c1svSDb49ZRAr8y2BTsW +UnbOQ04rrd53EBa1c/5/SX4wnnRUBUqYHPd2OyigzMTqpSD87RAj6buyrlhiauFPPqd S3eKGkiBZ8Mypy3jGMmLZ/vXxNz6yjafXyvW0F2bvzMPKCyHVjiphW3/qxQw6KHVa6nY lSVg== X-Gm-Message-State: AOJu0YxP7obYRlrahjJadtuNcRpNeTY1cklGd78AC5984E/BwH1xRetc tk2iCROamnHJK1vfj/vvxBMcbNhlxxnB72SPJQWb8oazM3C1VK6QH9U2F8cd X-Google-Smtp-Source: AGHT+IFAsR9ahUI3y+OceZKLRZtsJbREhCNARElu94LtcXJWVPKMvmNIJPKzh7NeQboMn8SZdMInXA== X-Received: by 2002:a17:903:244d:b0:20c:bb35:dae2 with SMTP id d9443c01a7336-210c69e1c8emr218143015ad.28.1730346842559; Wed, 30 Oct 2024 20:54:02 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Rob Bradford , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 12/50] target/riscv: Set vtype.vill on CPU reset Date: Thu, 31 Oct 2024 13:52:40 +1000 Message-ID: <20241031035319.731906-13-alistair.francis@wdc.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241031035319.731906-1-alistair.francis@wdc.com> References: <20241031035319.731906-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=alistair23@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1730346908368116600 Content-Type: text/plain; charset="utf-8" From: Rob Bradford The RISC-V unprivileged specification "31.3.11. State of Vector Extension at Reset" has a note that recommends vtype.vill be set on reset as part of ensuring that the vector extension have a consistent state at reset. This change now makes QEMU consistent with Spike which sets vtype.vill on reset. Signed-off-by: Rob Bradford Reviewed-by: Daniel Henrique Barboza Message-ID: <20240930165258.72258-1-rbradford@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0c8e017f71..2a78cd639b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1010,6 +1010,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetTy= pe type) cs->exception_index =3D RISCV_EXCP_NONE; env->load_res =3D -1; set_default_nan_mode(1, &env->fp_status); + env->vill =3D true; =20 #ifndef CONFIG_USER_ONLY if (cpu->cfg.debug) { --=20 2.47.0