31.10.2024 06:52, Alistair Francis wrote:
> ----------------------------------------------------------------
> RISC-V PR for 9.2
>
> * Fix an access to VXSAT
> * Expose RV32 cpu to RV64 QEMU
> * Don't clear PLIC pending bits on IRQ lowering
> * Make PLIC zeroth priority register read-only
> * Set vtype.vill on CPU reset
> * Check and update APLIC pending when write sourcecfg
> * Avoid dropping charecters with HTIF
> * Apply FIFO backpressure to guests using SiFive UART
> * Support for control flow integrity extensions
> * Support for the IOMMU with the virt machine
> * set 'aia_mode' to default in error path
> * clarify how 'riscv-aia' default works
Is there anything in there which is worth picking up for qemu-stable?
I see numerous "fixes" in there, but I'm not sure which is which and
what is important to have working in 9.1, 9.0, 8.2 (ubuntu lts) or 7.2...
(I've added some CCs)
Thanks,
/mjt
> ----------------------------------------------------------------
> Alistair Francis (2):
> hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all
> hw/char: sifive_uart: Print uart characters async
>
> Anton Blanchard (1):
> target/riscv: Fix vcompress with rvv_ta_all_1s
>
> Daniel Henrique Barboza (6):
> pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
> test/qtest: add riscv-iommu-pci tests
> qtest/riscv-iommu-test: add init queues test
> docs/specs: add riscv-iommu
> target/riscv/kvm: set 'aia_mode' to default in error path
> target/riscv/kvm: clarify how 'riscv-aia' default works
>
> Deepak Gupta (20):
> target/riscv: expose *envcfg csr and priv to qemu-user as well
> target/riscv: Add zicfilp extension
> target/riscv: Introduce elp state and enabling controls for zicfilp
> target/riscv: save and restore elp state on priv transitions
> target/riscv: additional code information for sw check
> target/riscv: tracking indirect branches (fcfi) for zicfilp
> target/riscv: zicfilp `lpad` impl and branch tracking
> disas/riscv: enable `lpad` disassembly
> target/riscv: Expose zicfilp extension as a cpu property
> target/riscv: Add zicfiss extension
> target/riscv: introduce ssp and enabling controls for zicfiss
> target/riscv: tb flag for shadow stack instructions
> target/riscv: mmu changes for zicfiss shadow stack protection
> target/riscv: AMO operations always raise store/AMO fault
> target/riscv: update `decode_save_opc` to store extra word2
> target/riscv: implement zicfiss instructions
> target/riscv: compressed encodings for sspush and sspopchk
> disas/riscv: enable disassembly for zicfiss instructions
> disas/riscv: enable disassembly for compressed sspush/sspopchk
> target/riscv: Expose zicfiss extension as a cpu property
>
> Evgenii Prokopiev (1):
> target/riscv/csr.c: Fix an access to VXSAT
>
> LIU Zhiwei (2):
> target/riscv: Add max32 CPU for RV64 QEMU
> tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU
>
> Rob Bradford (1):
> target/riscv: Set vtype.vill on CPU reset
>
> Sergey Makarov (2):
> hw/intc: Make zeroth priority register read-only
> hw/intc: Don't clear pending bits on IRQ lowering
>
> TANG Tiancheng (6):
> target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
> target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
> target/riscv: Correct SXL return value for RV32 in RV64 QEMU
> target/riscv: Detect sxl to set bit width for RV32 in RV64
> target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
> target/riscv: Enable RV32 CPU support in RV64 QEMU
>
> Tomasz Jeznach (8):
> exec/memtxattr: add process identifier to the transaction attributes
> hw/riscv: add riscv-iommu-bits.h
> hw/riscv: add RISC-V IOMMU base emulation
> hw/riscv: add riscv-iommu-pci reference device
> hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
> hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
> hw/riscv/riscv-iommu: add ATS support
> hw/riscv/riscv-iommu: add DBG support
>
> Yong-Xuan Wang (1):
> hw/intc/riscv_aplic: Check and update pending when write sourcecfg