From nobody Sat Nov 23 21:02:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1730215242; cv=none; d=zohomail.com; s=zohoarc; b=Y9/uA/aJM2eU54NNNvSR8C4p5k26GadGtkvwb0Oa5V22Dt0YzJJD+fLAziAG/TJsVKiEsibdHejg70Qpcg49WW1LXbLk4gHQk6N/I/2J4osfZXZC/7o2OIno1N6/AkNfKdQvU/SI4SaueTzF8SwzYWw3aA4v/W+66fQsj6xqaPg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730215242; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xl4RsPzTl9gqZQz0/OF4MHqmFAvJIOosnl1EsnMQjuA=; b=Z8S3G5Xm3GiCLYGlDHNaulRHnYcpGytGbu5AfyyHvm6p5tyOxPrsG2dn3bVgA0BDH8CejrzLQTCvW3erC6FJFI4rCcUXMJJErn6jjlb8nzOMC+U12hWtIj4GsxiWgC9IMvlLJJQESFd5IdsXphA8gvVion3KuJmaYDvBllrHqWg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1730215242957906.8284013684587; Tue, 29 Oct 2024 08:20:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t5o0L-0006UJ-83; Tue, 29 Oct 2024 11:19:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t5o08-0005lA-C7 for qemu-devel@nongnu.org; Tue, 29 Oct 2024 11:19:22 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t5o04-0000Qc-BS for qemu-devel@nongnu.org; Tue, 29 Oct 2024 11:19:20 -0400 Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-627-xpS_tTX_NcGpFHuAq_ZrOA-1; Tue, 29 Oct 2024 11:19:13 -0400 Received: by mail-wr1-f72.google.com with SMTP id ffacd0b85a97d-37d4d51b4efso2532846f8f.3 for ; Tue, 29 Oct 2024 08:19:13 -0700 (PDT) Received: from [192.168.10.3] ([151.49.226.83]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b0ea58sm12868467f8f.15.2024.10.29.08.19.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:19:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1730215154; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xl4RsPzTl9gqZQz0/OF4MHqmFAvJIOosnl1EsnMQjuA=; b=B6mlgpVAimzbheuALr92uAOBvqBnhgmwdjPG7pD/GgyneoCcZbLSxztZnunjigTRUzrN2b 4yAQQKyFIsljgsPXq0UhrULtIbT35gUnjoN/j6gV9AqCOF3634fbXfBLNfgzLwU4JKLolb LlylTA/KEiz22NwONBcY8w1VEBp5W7w= X-MC-Unique: xpS_tTX_NcGpFHuAq_ZrOA-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730215152; x=1730819952; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xl4RsPzTl9gqZQz0/OF4MHqmFAvJIOosnl1EsnMQjuA=; b=WeEuTwZNChXA13NabnIAnd8cBAViuCq7/yB5Fx3J8SdeaREggFcI6NeKMBlIat9s78 cZhalR5Yx6fAvYY3Rh2E3czrwk7tgze4aMkIlDDppYMC7BKr90E/Xaq/352iY9+8Yp7q E+92GCBKpkQmljA00WtOQFZgOme2NqLR/5ykzO+UkXwRnbW7Wlg0zfXv1LaNbbCXao7r jpCRD7PG/vmZ4CN2g2R+Isj1Km5VRlnOHlCyAorsCyCVry+qVvN/cGLW6oi+r74fWJVU x9brIuEY8OvS6PSF0IOzJ+Wd2EK+7RHDplJIq8k3ahjodJ8j9TXKsOjkp6dfYKtAFG1I XMew== X-Gm-Message-State: AOJu0YyTGp3wO/KzYGvZ2odS/YCaAJL1NnX488ujyuAd2JwyvMoc0zlv TPGZkR4UFOJnp3Zb9IRWP1OtrbVxTLczbnetw/XxBHql54FCToCWw9n5y0BzBKf+wXY3IvqpvGh OFLj7BJdA9u161Yp+6cxOGXQhpUf1FwJqn+0F+HEovl9S8zK/BHsIoEefHEknDXNz4WhqQWBscw zKPySP4BpBEZlatG6tY9KVySlpdPXYfCnj91aVQC8= X-Received: by 2002:adf:ce89:0:b0:37d:476d:2d58 with SMTP id ffacd0b85a97d-380611e56aemr8716814f8f.45.1730215151672; Tue, 29 Oct 2024 08:19:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH4wg9p2eEfzZsuqKc/Zds5oNZ1sCpx+RzELh5coGNHGtE/YZIBwyglL7sHISQKGja0zw+2HA== X-Received: by 2002:adf:ce89:0:b0:37d:476d:2d58 with SMTP id ffacd0b85a97d-380611e56aemr8716789f8f.45.1730215151160; Tue, 29 Oct 2024 08:19:11 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: tao1.su@linux.intel.com, zhao1.liu@intel.com, xiaoyao.li@intel.com Subject: [PATCH 4/8] target/i386: add AVX10 feature and AVX10 version property Date: Tue, 29 Oct 2024 16:18:54 +0100 Message-ID: <20241029151858.550269-5-pbonzini@redhat.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241029151858.550269-1-pbonzini@redhat.com> References: <20241029151858.550269-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.302, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1730215244899116600 Content-Type: text/plain; charset="utf-8" From: Tao Su When AVX10 enable bit is set, the 0x24 leaf will be present as "AVX10 Converged Vector ISA leaf" containing fields for the version number and the supported vector bit lengths. Introduce avx10-version property so that avx10 version can be controlled by user and cpu model. Per spec, avx10 version can never be 0, the default value of avx10-version is set to 0 to determine whether it is specified by user. The default can come from the device model or, for the max model, from KVM's reported value. Signed-off-by: Tao Su Link: https://lore.kernel.org/r/20241028024512.156724-3-tao1.su@linux.intel= .com Link: https://lore.kernel.org/r/20241028024512.156724-4-tao1.su@linux.intel= .com Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 4 +++ target/i386/cpu.c | 64 ++++++++++++++++++++++++++++++++++++++----- target/i386/kvm/kvm.c | 3 +- 3 files changed, 63 insertions(+), 8 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index a0a122cb5bf..72e98b25114 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -975,6 +975,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu= , FeatureWord w); #define CPUID_7_1_EDX_AMX_COMPLEX (1U << 8) /* PREFETCHIT0/1 Instructions */ #define CPUID_7_1_EDX_PREFETCHITI (1U << 14) +/* Support for Advanced Vector Extensions 10 */ +#define CPUID_7_1_EDX_AVX10 (1U << 19) /* Flexible return and event delivery (FRED) */ #define CPUID_7_1_EAX_FRED (1U << 17) /* Load into IA32_KERNEL_GS_BASE (LKGS) */ @@ -1954,6 +1956,8 @@ typedef struct CPUArchState { uint32_t cpuid_vendor3; uint32_t cpuid_version; FeatureWordArray features; + /* AVX10 version */ + uint8_t avx10_version; /* Features that were explicitly enabled/disabled */ FeatureWordArray user_features; uint32_t cpuid_model[12]; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c2f6045ec1c..fdbfcc59da4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -46,6 +46,9 @@ #include "cpu-internal.h" =20 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); +static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, + uint32_t *eax, uint32_t *ebx, + uint32_t *ecx, uint32_t *edx); =20 /* Helpers for building CPUID[2] descriptors: */ =20 @@ -1132,7 +1135,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { "avx-vnni-int8", "avx-ne-convert", NULL, NULL, "amx-complex", NULL, "avx-vnni-int16", NULL, NULL, NULL, "prefetchiti", NULL, - NULL, NULL, NULL, NULL, + NULL, NULL, NULL, "avx10", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, @@ -1989,6 +1992,7 @@ typedef struct X86CPUDefinition { int family; int model; int stepping; + int avx10_version; FeatureWordArray features; const char *model_id; const CPUCaches *const cache_info; @@ -5338,6 +5342,8 @@ static Property max_x86_cpu_properties[] =3D { static void max_x86_cpu_realize(DeviceState *dev, Error **errp) { Object *obj =3D OBJECT(dev); + X86CPU *cpu =3D X86_CPU(dev); + CPUX86State *env =3D &cpu->env; =20 if (!object_property_get_int(obj, "family", &error_abort)) { if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM= ) { @@ -5351,6 +5357,14 @@ static void max_x86_cpu_realize(DeviceState *dev, Er= ror **errp) } } =20 + if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10= _version) { + uint32_t eax, ebx, ecx, edx; + x86_cpu_get_supported_cpuid(0x24, 0, + &eax, &ebx, &ecx, &edx); + + env->avx10_version =3D ebx & 0xff; + } + x86_cpu_realizefn(dev, errp); } =20 @@ -6331,6 +6345,9 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUMod= el *model) */ object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abo= rt); =20 + object_property_set_int(OBJECT(cpu), "avx10-version", def->avx10_versi= on, + &error_abort); + x86_cpu_apply_version_props(cpu, model); =20 /* @@ -6859,6 +6876,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, } break; } + case 0x24: { + *eax =3D 0; + *ebx =3D 0; + *ecx =3D 0; + *edx =3D 0; + if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { + *ebx =3D env->avx10_version; + } + break; + } case 0x40000000: /* * CPUID code in kvm_arch_init_vcpu() ignores stuff @@ -7513,6 +7540,11 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **er= rp) x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); } =20 + /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ + if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); + } + /* SVM requires CPUID[0x8000000A] */ if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); @@ -7563,6 +7595,10 @@ static bool x86_cpu_filter_features(X86CPU *cpu, boo= l verbose) CPUX86State *env =3D &cpu->env; FeatureWord w; const char *prefix =3D NULL; + bool have_filtered_features; + + uint32_t eax_0, ebx_0, ecx_0, edx_0; + uint32_t eax_1, ebx_1, ecx_1, edx_1; =20 if (verbose) { prefix =3D accel_uses_host_cpuid() @@ -7584,13 +7620,10 @@ static bool x86_cpu_filter_features(X86CPU *cpu, bo= ol verbose) */ if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && kvm_enabled()) { - uint32_t eax_0, ebx_0, ecx_0, edx_0_unused; - uint32_t eax_1, ebx_1, ecx_1_unused, edx_1_unused; - x86_cpu_get_supported_cpuid(0x14, 0, - &eax_0, &ebx_0, &ecx_0, &edx_0_unused); + &eax_0, &ebx_0, &ecx_0, &edx_0); x86_cpu_get_supported_cpuid(0x14, 1, - &eax_1, &ebx_1, &ecx_1_unused, &edx_1_= unused); + &eax_1, &ebx_1, &ecx_1, &edx_1); =20 if (!eax_0 || ((ebx_0 & INTEL_PT_MINIMAL_EBX) !=3D INTEL_PT_MINIMAL_EBX) || @@ -7611,7 +7644,23 @@ static bool x86_cpu_filter_features(X86CPU *cpu, boo= l verbose) } } =20 - return x86_cpu_have_filtered_features(cpu); + have_filtered_features =3D x86_cpu_have_filtered_features(cpu); + + if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { + x86_cpu_get_supported_cpuid(0x24, 0, + &eax_0, &ebx_0, &ecx_0, &edx_0); + uint8_t version =3D ebx_0 & 0xff; + + if (version < env->avx10_version) { + if (prefix) { + warn_report("%s: avx10.%d", prefix, env->avx10_version); + } + env->avx10_version =3D version; + have_filtered_features =3D true; + } + } + + return have_filtered_features; } =20 static void x86_cpu_hyperv_realize(X86CPU *cpu) @@ -8395,6 +8444,7 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), + DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_leve= l, true), DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index fd9f1988920..8e17942c3ba 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1923,7 +1923,8 @@ static uint32_t kvm_x86_build_cpuid(CPUX86State *env, case 0x7: case 0x14: case 0x1d: - case 0x1e: { + case 0x1e: + case 0x24: { uint32_t times; =20 c->function =3D i; --=20 2.47.0