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Tue, 29 Oct 2024 08:19:05 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH4saYzE0tgf9mYzcF9FdC3vqsQk/xuOLBYideCq6dfXxsx0z+qYlzuVvewOADuaXryxD8bbg== X-Received: by 2002:a05:6512:12d1:b0:539:fcba:cc6d with SMTP id 2adb3069b0e04-53b34a19019mr5150137e87.42.1730215144603; Tue, 29 Oct 2024 08:19:04 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: tao1.su@linux.intel.com, zhao1.liu@intel.com, xiaoyao.li@intel.com Subject: [PATCH 2/8] target/i386: do not rely on ExtSaveArea for accelerator-supported XCR0 bits Date: Tue, 29 Oct 2024 16:18:52 +0100 Message-ID: <20241029151858.550269-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241029151858.550269-1-pbonzini@redhat.com> References: <20241029151858.550269-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.302, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1730215212925116600 Content-Type: text/plain; charset="utf-8" Right now, QEMU is using the "feature" and "bits" fields of ExtSaveArea to query the accelerator for the support status of extended save areas. This is a problem for AVX10, which attaches two feature bits (AVX512F and AVX10) to the same extended save states. To keep the AVX10 hacks to the minimum, limit usage of esa->features and esa->bits. Instead, just query the accelerator for the 0xD leaf. Do it in common code and clear esa->size if an extended save state is unsupported. Signed-off-by: Paolo Bonzini Reviewed-by: Zhao Liu --- target/i386/cpu.c | 33 +++++++++++++++++++++++++++++++-- target/i386/kvm/kvm-cpu.c | 4 ---- 2 files changed, 31 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f08e9b8f1bc..1ee4d988caf 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7102,6 +7102,15 @@ static void x86_cpu_set_sgxlepubkeyhash(CPUX86State = *env) #endif } =20 +static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *e= sa) +{ + if (!esa->size) { + return false; + } + + return (env->features[esa->feature] & esa->bits); +} + static void x86_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); @@ -7210,7 +7219,7 @@ static void x86_cpu_reset_hold(Object *obj, ResetType= type) if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { continue; } - if (env->features[esa->feature] & esa->bits) { + if (cpuid_has_xsave_feature(env, esa)) { xcr0 |=3D 1ull << i; } } @@ -7348,7 +7357,7 @@ static void x86_cpu_enable_xsave_components(X86CPU *c= pu) mask =3D 0; for (i =3D 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { const ExtSaveArea *esa =3D &x86_ext_save_areas[i]; - if (env->features[esa->feature] & esa->bits) { + if (cpuid_has_xsave_feature(env, esa)) { mask |=3D (1ULL << i); } } @@ -8020,6 +8029,26 @@ static void x86_cpu_register_feature_bit_props(X86CP= UClass *xcc, =20 static void x86_cpu_post_initfn(Object *obj) { + static bool first =3D true; + uint64_t supported_xcr0; + int i; + + if (first) { + first =3D false; + + supported_xcr0 =3D + ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAV= E_XCR0_HI) << 32) | + x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO); + + for (i =3D XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) { + ExtSaveArea *esa =3D &x86_ext_save_areas[i]; + + if (!(supported_xcr0 & (1 << i))) { + esa->size =3D 0; + } + } + } + accel_cpu_instance_init(CPU(obj)); } =20 diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index 6bf8dcfc607..d9306418490 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -133,10 +133,6 @@ static void kvm_cpu_xsave_init(void) if (!esa->size) { continue; } - if ((x86_cpu_get_supported_feature_word(NULL, esa->feature) & esa-= >bits) - !=3D esa->bits) { - continue; - } host_cpuid(0xd, i, &eax, &ebx, &ecx, &edx); if (eax !=3D 0) { assert(esa->size =3D=3D eax); --=20 2.47.0