From nobody Sat Nov 23 19:48:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1730193550; cv=none; d=zohomail.com; s=zohoarc; b=S4LaN2q8VltVjHnQ7EQrMYLgb2epHl/eb/Qiejs+v5gQBBUHKfx8djb1xYAhkB+S+b85/dV06fsQAp2KAAUG2YMWr9raXLvafgFpi2qFRrO8Iiv8WCMhHjQQkFB84j/w0XnfsByrpAxDaGdUQGUqvieWxOKwD+dlH9i3uqH5sHU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730193550; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=gV1O5Rb7blVfbi2RD7rwG4QbWvEX0MzbQQ1ZITjqVKg=; b=gLUjvMVOn84M7+55Eep+W/uZOMH8QUSwg5pUQ+z1GUDG6apwQIlTTUZIPfrDnllY64AhlYqrpgDPq2pbCnKoLj3/jNcotSndqqvaf9+MQdc3ui1YgdGVR1XQ0DLNE8gU7i6J+Q8EMfY1mUP2UIYeeVk8VqubbcDNiWGsNEiPre8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1730193550811249.85598786215303; Tue, 29 Oct 2024 02:19:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t5iMh-0000ho-Ii; Tue, 29 Oct 2024 05:18:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t5iMM-0000aR-Io; Tue, 29 Oct 2024 05:17:54 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t5iMJ-0003A3-SA; Tue, 29 Oct 2024 05:17:53 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 29 Oct 2024 17:17:31 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 29 Oct 2024 17:17:31 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:SD (Secure Card)" CC: , , Subject: [PATCH v1 5/8] hw/sd/sdhci: Introduce a new Write Protected pin inverted property Date: Tue, 29 Oct 2024 17:17:26 +0800 Message-ID: <20241029091729.3317512-6-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029091729.3317512-1-jamin_lin@aspeedtech.com> References: <20241029091729.3317512-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1730193553159116600 Content-Type: text/plain; charset="utf-8" The Write Protect pin of SDHCI model is default active low to match the SDH= CI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). However, some board are design Write Protected pin active high. In other words, write enable the bi= t 19 should be 0 and write protected the bit 19 should be 1 at the Present State Register (0x24). To support it, introduces a new "wp_invert" property and set it false by default. Signed-off-by: Jamin Lin --- hw/sd/sdhci.c | 6 ++++++ include/hw/sd/sdhci.h | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index db7d547156..bdf5cbfb80 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -275,6 +275,10 @@ static void sdhci_set_readonly(DeviceState *dev, bool = level) { SDHCIState *s =3D (SDHCIState *)dev; =20 + if (s->wp_invert) { + level =3D !level; + } + if (level) { s->prnsts &=3D ~SDHC_WRITE_PROTECT; } else { @@ -1551,6 +1555,8 @@ static Property sdhci_sysbus_properties[] =3D { false), DEFINE_PROP_LINK("dma", SDHCIState, dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_BOOL("wp-invert", SDHCIState, + wp_invert, false), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 6cd2822f1d..d68f4788e7 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -100,6 +100,11 @@ struct SDHCIState { uint8_t sd_spec_version; uint8_t uhs_mode; uint8_t vendor; /* For vendor specific functionality */ + /* + * Write Protect pin default active low for detecting SD card + * to be protected. Set wp_invert to true inverted the signal. + */ + bool wp_invert; }; typedef struct SDHCIState SDHCIState; =20 --=20 2.34.1