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Tue, 29 Oct 2024 17:17:31 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 29 Oct 2024 17:17:31 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:SD (Secure Card)" CC: , , Subject: [PATCH v1 4/8] hw/sd/sdhci: Fix coding style Date: Tue, 29 Oct 2024 17:17:25 +0800 Message-ID: <20241029091729.3317512-5-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029091729.3317512-1-jamin_lin@aspeedtech.com> References: <20241029091729.3317512-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1730193628337116600 Content-Type: text/plain; charset="utf-8" Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/sd/sdhci.c | 64 +++++++++++++++++++++++++++++++++------------------ 1 file changed, 42 insertions(+), 22 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index ed01499391..db7d547156 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -234,7 +234,7 @@ static void sdhci_raise_insertion_irq(void *opaque) =20 if (s->norintsts & SDHC_NIS_REMOVE) { timer_mod(s->insert_timer, - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERT= ION_DELAY); + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DEL= AY); } else { s->prnsts =3D 0x1ff0000; if (s->norintstsen & SDHC_NISEN_INSERT) { @@ -252,7 +252,7 @@ static void sdhci_set_inserted(DeviceState *dev, bool l= evel) if ((s->norintsts & SDHC_NIS_REMOVE) && level) { /* Give target some time to notice card ejection */ timer_mod(s->insert_timer, - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERT= ION_DELAY); + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DEL= AY); } else { if (level) { s->prnsts =3D 0x1ff0000; @@ -290,9 +290,11 @@ static void sdhci_reset(SDHCIState *s) timer_del(s->insert_timer); timer_del(s->transfer_timer); =20 - /* Set all registers to 0. Capabilities/Version registers are not clea= red + /* + * Set all registers to 0. Capabilities/Version registers are not clea= red * and assumed to always preserve their value, given to them during - * initialization */ + * initialization + */ memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmas= ysad); =20 /* Reset other state based on current card insertion/readonly status */ @@ -306,7 +308,8 @@ static void sdhci_reset(SDHCIState *s) =20 static void sdhci_poweron_reset(DeviceState *dev) { - /* QOM (ie power-on) reset. This is identical to reset + /* + * QOM (ie power-on) reset. This is identical to reset * commanded via device register apart from handling of the * 'pending insert on powerup' quirk. */ @@ -446,8 +449,10 @@ static void sdhci_read_block_from_card(SDHCIState *s) s->prnsts &=3D ~SDHC_DAT_LINE_ACTIVE; } =20 - /* If stop at block gap request was set and it's not the last block of - * data - generate Block Event interrupt */ + /* + * If stop at block gap request was set and it's not the last block of + * data - generate Block Event interrupt + */ if (s->stopped_state =3D=3D sdhc_gap_read && (s->trnmod & SDHC_TRNS_MU= LTI) && s->blkcnt !=3D 1) { s->prnsts &=3D ~SDHC_DAT_LINE_ACTIVE; @@ -549,8 +554,10 @@ static void sdhci_write_block_to_card(SDHCIState *s) sdhci_update_irq(s); } =20 -/* Write @size bytes of @value data to host controller @s Buffer Data Port - * register */ +/* + * Write @size bytes of @value data to host controller @s Buffer Data Port + * register + */ static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned s= ize) { unsigned i; @@ -595,9 +602,11 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIStat= e *s) return; } =20 - /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account f= or + /* + * XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account f= or * possible stop at page boundary if initial address is not page align= ed, - * allow them to work properly */ + * allow them to work properly + */ if ((s->sdmasysad % boundary_chk) =3D=3D 0) { page_aligned =3D true; } @@ -703,7 +712,8 @@ static void get_adma_description(SDHCIState *s, ADMADes= cr *dscr) dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2), MEMTXATTRS_UNSPECIFIED); adma2 =3D le64_to_cpu(adma2); - /* The spec does not specify endianness of descriptor table. + /* + * The spec does not specify endianness of descriptor table. * We currently assume that it is LE. */ dscr->addr =3D (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; @@ -978,8 +988,10 @@ static bool sdhci_can_issue_command(SDHCIState *s) return true; } =20 -/* The Buffer Data Port register must be accessed in sequential and - * continuous manner */ +/* + * The Buffer Data Port register must be accessed in sequential and + * continuous manner + */ static inline bool sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) { @@ -1207,8 +1219,10 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t va= l, unsigned size) MASKED_WRITE(s->argument, mask, value); break; case SDHC_TRNMOD: - /* DMA can be enabled only if it is supported as indicated by - * capabilities register */ + /* + * DMA can be enabled only if it is supported as indicated by + * capabilities register + */ if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { value &=3D ~SDHC_TRNS_DMA; } @@ -1280,8 +1294,10 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t va= l, unsigned size) } else { s->norintsts &=3D ~SDHC_NIS_ERR; } - /* Quirk for Raspberry Pi: pending card insert interrupt - * appears when first enabled after power on */ + /* + * Quirk for Raspberry Pi: pending card insert interrupt + * appears when first enabled after power on + */ if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_stat= e) { assert(s->pending_insert_quirk); s->norintsts |=3D SDHC_NIS_INSERT; @@ -1397,8 +1413,10 @@ void sdhci_initfn(SDHCIState *s) { qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SDHCI_BUS, DEVICE(s), "sd-= bus"); =20 - s->insert_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_inser= tion_irq, s); - s->transfer_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_tran= sfer, s); + s->insert_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + sdhci_raise_insertion_irq, s); + s->transfer_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + sdhci_data_transfer, s); =20 s->io_ops =3D &sdhci_mmio_le_ops; } @@ -1446,11 +1464,13 @@ void sdhci_common_realize(SDHCIState *s, Error **er= rp) =20 void sdhci_common_unrealize(SDHCIState *s) { - /* This function is expected to be called only once for each class: + /* + * This function is expected to be called only once for each class: * - SysBus: via DeviceClass->unrealize(), * - PCI: via PCIDeviceClass->exit(). * However to avoid double-free and/or use-after-free we still nullify - * this variable (better safe than sorry!). */ + * this variable (better safe than sorry!). + */ g_free(s->fifo_buffer); s->fifo_buffer =3D NULL; } --=20 2.34.1