From nobody Sat Nov 23 20:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1730193514; cv=none; d=zohomail.com; s=zohoarc; b=HnR5YvoVs6GL1Z4Hm0XvEN1WvxLJvxLDPAf0yjnDJJs1Rr+vMMftrUkMD26GeySCLNl7/5Soo3ZFikBBdxoHjB/6sPvkWvhZLtywPBNA19SbI0W9Fiwr7Z+Fh1VfcSbkkQ8TRi0iSgIKDE213FxA20IDyzEnhadYoqqZknTEa4c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730193514; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=I6b8ZfEbINB6Js0mAvDW78IC2X6VREHK+mCncE394Cc=; b=mzF2DYIvQZK6vUj40IZ1u56FLwNfpHlSZxWgGbNyrTTn8bH5Xf1osutSx9ttE7O0yxZgtDg9y47GQhu4ixo6fgX7Obx5I66pps3C+d62LN2mKv6qoco4H3WeHHTJ5rOMlRZ+bNgMW7/so4iuJZT5lfMdDPiTW4zh6LsTGyrLE+I= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1730193514319970.2308014821427; Tue, 29 Oct 2024 02:18:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t5iMJ-0000Zf-3c; Tue, 29 Oct 2024 05:17:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t5iMG-0000YE-0F; Tue, 29 Oct 2024 05:17:48 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t5iME-0003A3-Pd; Tue, 29 Oct 2024 05:17:47 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 29 Oct 2024 17:17:30 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 29 Oct 2024 17:17:30 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:SD (Secure Card)" CC: , , Subject: [PATCH v1 3/8] hw/timer/aspeed: Fix interrupt status does not be cleared for AST2600 Date: Tue, 29 Oct 2024 17:17:24 +0800 Message-ID: <20241029091729.3317512-4-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029091729.3317512-1-jamin_lin@aspeedtech.com> References: <20241029091729.3317512-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1730193516242116600 Content-Type: text/plain; charset="utf-8" According to the datasheet of AST2600 description, interrupt status set by = HW and clear to "0" by software writing "1" on the specific bit. Therefore, if firmware set the specific bit "1" in the interrupt status register(0x34), the specific bit of "s->irq_sts" should be cleared 0. Signed-off-by: Jamin Lin Reviewed-by: Andrew Jeffery Reviewed-by: C=C3=A9dric Le Goater --- hw/timer/aspeed_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 5af268ea9e..149f7cc5a6 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -580,7 +580,7 @@ static void aspeed_2600_timer_write(AspeedTimerCtrlStat= e *s, hwaddr offset, =20 switch (offset) { case 0x34: - s->irq_sts &=3D tv; + s->irq_sts &=3D ~tv; break; case 0x3C: aspeed_timer_set_ctrl(s, s->ctrl & ~tv); --=20 2.34.1