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Mon, 28 Oct 2024 08:19:07 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGAKqsJN6Tzd9N+SRqNC2dpxVOGUpL89zCdQDCrsg5ovEh/1JYCQCr9M6fMPCj/8wtY67/OSQ== X-Received: by 2002:a05:6512:3f07:b0:535:6a4d:ed74 with SMTP id 2adb3069b0e04-53b34b370d4mr4074783e87.51.1730128746592; Mon, 28 Oct 2024 08:19:06 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org Subject: [PATCH 03/14] target/i386: remove CC_OP_CLR Date: Mon, 28 Oct 2024 16:18:40 +0100 Message-ID: <20241028151851.376355-4-pbonzini@redhat.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241028151851.376355-1-pbonzini@redhat.com> References: <20241028151851.376355-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.373, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1730128887129116600 Content-Type: text/plain; charset="utf-8" Just use CC_OP_EFLAGS; it is not that likely that the flags computed by CC_OP_CLR survive the end of the basic block, in which case there is no need to spill cc_op_src. cc_op_src now does need spilling if the XOR is followed by a memory operation, but this only costs 0.2% extra TCG ops. They will be recouped by simplifications in how QEMU evaluates ZF at runtime, which are even greater with this change. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 1 - target/i386/cpu-dump.c | 1 - target/i386/tcg/cc_helper.c | 3 --- target/i386/tcg/translate.c | 10 ---------- target/i386/tcg/emit.c.inc | 15 ++++----------- 5 files changed, 4 insertions(+), 26 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e4c947b478b..c89db50eddc 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1297,7 +1297,6 @@ typedef enum { CC_OP_ADCX, /* CC_DST =3D C, CC_SRC =3D rest. */ CC_OP_ADOX, /* CC_SRC2 =3D O, CC_SRC =3D rest. */ CC_OP_ADCOX, /* CC_DST =3D C, CC_SRC2 =3D O, CC_SRC =3D rest. */ - CC_OP_CLR, /* Z and P set, all other flags clear. */ =20 CC_OP_MULB, /* modify all flags, C, O =3D (CC_SRC !=3D 0) */ CC_OP_MULW, diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c index dc6723aedee..a72ed93bd2f 100644 --- a/target/i386/cpu-dump.c +++ b/target/i386/cpu-dump.c @@ -91,7 +91,6 @@ static const char * const cc_op_str[] =3D { [CC_OP_BMILGQ] =3D "BMILGQ", =20 [CC_OP_POPCNT] =3D "POPCNT", - [CC_OP_CLR] =3D "CLR", }; =20 static void diff --git a/target/i386/tcg/cc_helper.c b/target/i386/tcg/cc_helper.c index dbddaa2fcb3..40583c04cf9 100644 --- a/target/i386/tcg/cc_helper.c +++ b/target/i386/tcg/cc_helper.c @@ -104,8 +104,6 @@ target_ulong helper_cc_compute_all(target_ulong dst, ta= rget_ulong src1, =20 case CC_OP_EFLAGS: return src1; - case CC_OP_CLR: - return CC_Z | CC_P; case CC_OP_POPCNT: return dst ? 0 : CC_Z; =20 @@ -243,7 +241,6 @@ target_ulong helper_cc_compute_c(target_ulong dst, targ= et_ulong src1, case CC_OP_LOGICW: case CC_OP_LOGICL: case CC_OP_LOGICQ: - case CC_OP_CLR: case CC_OP_POPCNT: return 0; =20 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index dc308f31041..a20fbb019c8 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -309,7 +309,6 @@ static const uint8_t cc_op_live[CC_OP_NB] =3D { [CC_OP_ADCX] =3D USES_CC_DST | USES_CC_SRC, [CC_OP_ADOX] =3D USES_CC_SRC | USES_CC_SRC2, [CC_OP_ADCOX] =3D USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, - [CC_OP_CLR] =3D 0, [CC_OP_POPCNT] =3D USES_CC_DST, }; =20 @@ -803,10 +802,6 @@ static void gen_mov_eflags(DisasContext *s, TCGv reg) tcg_gen_mov_tl(reg, cpu_cc_src); return; } - if (s->cc_op =3D=3D CC_OP_CLR) { - tcg_gen_movi_tl(reg, CC_Z | CC_P); - return; - } =20 dst =3D cpu_cc_dst; src1 =3D cpu_cc_src; @@ -897,7 +892,6 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, = TCGv reg) .reg2 =3D cpu_cc_src, .use_reg2 =3D true }; =20 case CC_OP_LOGICB ... CC_OP_LOGICQ: - case CC_OP_CLR: case CC_OP_POPCNT: return (CCPrepare) { .cond =3D TCG_COND_NEVER }; =20 @@ -969,7 +963,6 @@ static CCPrepare gen_prepare_eflags_s(DisasContext *s, = TCGv reg) case CC_OP_ADCOX: return (CCPrepare) { .cond =3D TCG_COND_TSTNE, .reg =3D cpu_cc_src, .imm =3D CC_S }; - case CC_OP_CLR: case CC_OP_POPCNT: return (CCPrepare) { .cond =3D TCG_COND_NEVER }; default: @@ -988,7 +981,6 @@ static CCPrepare gen_prepare_eflags_o(DisasContext *s, = TCGv reg) case CC_OP_ADCOX: return (CCPrepare) { .cond =3D TCG_COND_NE, .reg =3D cpu_cc_src2, .no_setcond =3D true }; - case CC_OP_CLR: case CC_OP_POPCNT: return (CCPrepare) { .cond =3D TCG_COND_NEVER }; case CC_OP_MULB ... CC_OP_MULQ: @@ -1013,8 +1005,6 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s= , TCGv reg) case CC_OP_ADCOX: return (CCPrepare) { .cond =3D TCG_COND_TSTNE, .reg =3D cpu_cc_src, .imm =3D CC_Z }; - case CC_OP_CLR: - return (CCPrepare) { .cond =3D TCG_COND_ALWAYS }; default: { MemOp size =3D (s->cc_op - CC_OP_ADDB) & 3; diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index fd17a9b1eca..790307dbba8 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1452,19 +1452,12 @@ static void gen_bt_flags(DisasContext *s, X86Decode= dInsn *decode, TCGv src, TCGv * C is the result of the test, Z is unchanged, and the others * are all undefined. */ - switch (s->cc_op) { - case CC_OP_DYNAMIC: - case CC_OP_CLR: - case CC_OP_EFLAGS: - case CC_OP_ADCX: - case CC_OP_ADOX: - case CC_OP_ADCOX: + if (s->cc_op =3D=3D CC_OP_DYNAMIC || CC_OP_HAS_EFLAGS(s->cc_op)) { /* Generate EFLAGS and replace the C bit. */ cf =3D tcg_temp_new(); tcg_gen_setcond_tl(TCG_COND_TSTNE, cf, src, mask); prepare_update_cf(decode, s, cf); - break; - default: + } else { /* * Z was going to be computed from the non-zero status of CC_DST. * We can get that same Z value (and the new C value) by leaving @@ -1475,7 +1468,6 @@ static void gen_bt_flags(DisasContext *s, X86DecodedI= nsn *decode, TCGv src, TCGv decode->cc_dst =3D cpu_cc_dst; decode->cc_op =3D ((s->cc_op - CC_OP_MULB) & 3) + CC_OP_SARB; tcg_gen_shr_tl(decode->cc_src, src, s->T1); - break; } } =20 @@ -4724,7 +4716,8 @@ static void gen_XOR(DisasContext *s, X86DecodedInsn *= decode) decode->op[2].unit =3D=3D X86_OP_INT && decode->op[1].n =3D=3D decode->op[2].n) { tcg_gen_movi_tl(s->T0, 0); - decode->cc_op =3D CC_OP_CLR; + decode->cc_op =3D CC_OP_EFLAGS; + decode->cc_src =3D tcg_constant_tl(CC_Z | CC_P); } else { MemOp ot =3D decode->op[1].ot; =20 --=20 2.47.0